NM25C020 2048-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
NM25C020
June 1997
NM25C020
2048-Bit Serial CMOS EEPROM (Serial Peripheral
Interface (SPI
™
) Synchronous Bus)
General Description
The NM25C020 is a 2048-bit CMOS EEPROM with a SPI
compatible serial interface. The NM25C020 is designed for
data storage in applications requiring both nonvolatile
memory and in-system data updates. This EEPROM is well
suited for applications using the 68HC11 series of microcon-
trollers that support the SPI interface for high speed commu-
nication with peripheral devices via a serial bus to reduce pin
count. The NM25C020 is implemented in Fairchild Semicon-
ductor’s floating gate CMOS process that provides superior
endurance and data retention.
The serial data transmission of this device requires four sig-
nal lines to control the device operation: Chip Select (CS ),
Clock (SCK), Serial Data In (SI), and Serial Data Out (SO).
All programming cycles are completely self-timed and do not
require an erase before WRITE.
BLOCK WRITE protection is provided by programming the
STATUS REGISTER with one of four levels of write protec-
tion. Additionally, separate write enable and write disable in-
structions are provided for data protection.
Hardware data protection is provided by the WP pin to pro-
tect against accidental data changes. The HOLD pin allows
the serial communication to be suspended without resetting
the serial sequence.
Features
n
2.1 MHz clock rate
n
2048-bits organized as 256 x 8
n
Multiple chips on the same 3-wire bus with separate
chip select lines
n
Self-timed programming cycle
n
Simultaneous programming of 1 to 4 bytes at a time
n
Status register can be polled during programming to
monitor READY/BUSY
n
Write Protect (WP ) pin and write disable instruction for
both hardware and software write protection
n
Block write protect feature to protect against accidental
writes
n
Endurance: 10
6
data changes
n
Data retention greater than 40 years
n
Packages available: 8-Pin DIP, 8-Pin SO or 8-Pin
TSSOP
Block Diagram
DS012400-1
SPI
™
is a trademark of Motorola, Inc.
© 1997 Fairchild Semiconductor Corporation
DS012400
www.fairchildsemi.com
1
PrintDate=1997/08/04 PrintTime=17:25:43 5250 ds012400 Rev. No. 5
cmserv
Proof
1
Connection Diagram
Dual-In-Line Package (N)
SO Package (M8) and
TSSOP Package (MT8)
DS012400-2
Top View
See Package Number
N08E (N), M08A (M8) and MTC08 (MT8)
Pin Names
CS
SO
WP
V
SS
SI
SCK
HOLD
V
CC
Chip Select Input
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock Input
Suspends Serial Input
Power Supply
Ordering Information
Commercial Temperature Range (0˚C to +70˚C)
Order Number
NM25C020N/LN/LZN
NM25C020M8/LM8/LZM8
NM25C020MT8/LMT8/LZMT8
Extended Temperature Range (−40˚C to +85˚C)
Order Number
NM25C020EN/LEN/LZEN
NM25C020EM8/LEM8/LZEM8
NM25C020EMT8/LEMT8/LZEMT8
Automotive Temperature Range (−40˚C to +125˚C)
Order Number
NM25C020VN/LVN/LZVN
NM25C020VM8/LVM8/LZVM8
NM25C020VMT8/LVMT8/LZVMT8
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PrintDate=1997/08/04 PrintTime=17:25:45 5250 ds012400 Rev. No. 5 cmserv
Proof
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Standard Voltage 4.5V
≤
V
CC
≤
5.5V Specifications
Absolute Maximum Ratings
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 seconds)
(Note 1)
−65˚C to +150˚C
+6.5V to −0.3V
+300˚C
ESD Rating
2000V
Operating Conditions
Ambient Operating Temperature
NM25C020
NM25C020E
NM25C020V
Power Supply (V
CC
)
0˚C to +70˚C
−40˚C to +85˚C
−40˚C to +125˚C
4.5V–5.5V
DC and AC Electrical Characteristics
Symbol
I
CC
I
CCSB
I
IL
I
OL
V
IL
V
IH
V
OL
V
OH
f
OP
t
RI
t
FI
t
CLH
t
CLL
t
CSH
t
CSS
t
DIS
t
HDS
t
CSN
t
DIN
t
HDN
t
PD
t
LZ
t
DF
t
HZ
t
WP
Parameter
Operating Current
Standby Current
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SCK Frequency
Input Rise Time
Input Fall Time
Clock High Time
Clock Low Time
Minimum CS High Time
CS Setup Time
Data Setup Time
HOLD Setup Time
CS Hold Time
Data Hold Time
HOLD Hold Time
Output Delay
HOLD Output Low Z
Output Disable Time
HOLD to Output High Z
Write Cycle Time
NM25C020
NM25C020
NM25C020
NM25C020
1–4 Bytes
C
L
= 200 pF
C
L
= 200 pF
NM25C020
NM25C020
NM25C020
NM25C020
NM25C020
NM25C020
(Note 2)
(Note 2)
(Note 3)
190
190
240
240
100
90
240
100
90
240
100
240
100
10
NM25C020
I
OL
= 1.6 mA
I
OH
= −0.8 mA
Part Number
Conditions
CS = V
IL
CS = V
CC
V
IN
= 0 to V
CC
V
OUT
= GND to V
CC
Min
Max
3
50
−1
−1
−0.3
0.7
*
V
CC
V
CC
− 0.8
2.1
2.0
2.0
1
+1
V
CC
*
0.3
V
CC
+ 0.3
0.4
Units
mA
µA
µA
µA
V
V
V
V
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Capacitance
T
A
= 25˚C, f = 1 MHz
Symbol
C
OUT
C
IN
Test
Output Capacitance
Input Capacitance
Type
3
2
Max
8
6
Units
pF
pF
AC Test Conditions
Output Load
Input Pulse Levels
Timing Measurement
Reference Level
0.3
*
V
CC
– 0.7
*
V
CC
C
L
= 200 pF
0.1
*
V
CC
– 0.9
*
V
CC
Note 1:
Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional op-
eration of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect device reliability.
Note 2:
The SCK frequency specification specifies a minimum clock period of 476 ns; therefore, in a SCK clock cycle, t
CLH
+ t
CLL
must be
≥476
ns. For example,
if t
CLL
= 190 ns, then the minimum t
CLH
= 286 ns in order to meet the SCK frequency specification.
Note 3:
CS must be brought high for a minimum of 240 ns (t
CSH
) between consecutive instruction cycles.
3
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PrintDate=1997/08/04 PrintTime=17:25:48 5250 ds012400 Rev. No. 5 cmserv
Proof
3
Low Voltage 2.7V
≤
V
CC
≤
5.5V
Specifications
Absolute Maximum Ratings
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 seconds)
(Note 4)
−65˚C to +150˚C
+6.5V to −0.3V
+300˚C
ESD Rating
2000V
Operating Conditions
Ambient Operating Temperature
NM25C020L/LZ
NM25C020LE/LZE
NM25C020LV/LZV
Power Supply (V
CC
)
0˚C to +70˚C
−40˚C to +85˚C
−40˚C to +125˚C
2.7V–5.5V
DC and AC Electrical Characteristics
Symbol
I
CC
I
CCSB
I
IL
I
OL
V
IL
V
IH
V
OL
V
OH
f
OP
t
RI
t
FI
t
CLH
t
CLL
t
CSH
t
CSS
t
DIS
t
HDS
t
CSN
t
DIN
t
HDN
t
PD
t
LZ
t
DF
t
HZ
t
WP
Parameter
Operating Current
Standby Current
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SCK Frequency
Input Rise Time
Input Fall Time
Clock High Time
Clock Low Time
Minimum CS High Time
CS Setup Time
Data Setup Time
HOLD Setup Time
CS Hold Time
Data Hold Time
HOLD Hold Time
Output Delay
HOLD Output Low Z
Output Disable Time
HOLD to Output High Z
Write Cycle Time
1–4 Bytes
C
L
= 200 pF
C
L
= 200 pF
(Note 5)
(Note 5)
(Note 6)
410
410
500
500
100
240
500
100
240
500
240
500
240
10
I
OL
= 0.8 mA
I
OH
= −0.4 mA
Z
LZ
V
IN
= 0 to V
CC
V
OUT
= GND to V
CC
−1
−0.3
0.7
*
V
CC
V
CC
− 0.8
1
2.0
2.0
Part Number
Conditions
CS = V
IL
CS = V
CC
Min
Max
3
10
1
+1
+1
0.3
*
V
CC
V
CC
+ 0.3
0.4
Units
mA
µA
µA
µA
V
V
V
V
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Capacitance
T
A
= 25˚C, f = 1 MHz
Symbol
C
OUT
C
IN
Test
Output Capacitance
Input Capacitance
Type
3
2
Max
8
6
Units
pF
pF
AC Test Conditions
Output Load
Input Pulse Levels
Timing Measurement
Reference Level
0.3
*
V
CC
– 0.7
*
V
CC
C
L
= 200 pF
0.1
*
V
CC
− 0.9
*
V
CC
Note 4:
Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional op-
eration of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect device reliability.
Note 5:
The SCK frequency specification specifies a minimum clock period of 476 ns; therefore, in a SCK clock cycle, t
CLH
+ t
CLL
must be
≥476
ns. For example,
if t
CLL
= 190 ns, then the minimum t
CLH
= 286 ns in order to meet the SCK frequency specification.
Note 6:
CS must be brought high for a minimum of 240 ns (t
CSH
) between consecutive instruction cycles.
www.fairchildsemi.com
4
PrintDate=1997/08/04 PrintTime=17:25:51 5250 ds012400 Rev. No. 5 cmserv
Proof
4
AC Test Conditions
(Continued)
DS012400-3
FIGURE 1. Synchronous Data Timing Diagram
DS012400-4
Note:
When connected to the SPI port of a 68HC11 microcontroller, the NM25C020 accepts a clock phase of 0 and a clock parity of 0.
FIGURE 2. SPI Serial Interface
5
www.fairchildsemi.com
PrintDate=1997/08/04 PrintTime=17:25:52 5250 ds012400 Rev. No. 5 cmserv
Proof
5
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