ZL40518
3 Channel Laser Diode Driver
Data Sheet
Features
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•
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•
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Current-controlled Output Current source
Output Current per Channel to 250 mA
Total Output Current to 300 mA
Rise Time 1.0 ns, Fall Time 1.1 ns
On-chip RF Oscillator
External Resistor Control of Oscillator Swing and
Frequency
200 to 500 MHz Oscillator Range
100 mA Maximum Oscillator Swing
Single +5 V Power Supply (±10%)
Low-power Consumption
Common Enable, Disable Input
TTL/CMOS control signals
Small SS016 Package
Ordering Information
ZL40518DGE1
16 Pin QSOP*
*Pb Free Matte Tin
0°C to +70°C
Tubes
February 2005
Applications
•
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DVD R/RW
CD R/RW
CH_R
INR
/ENR
CH_2
IN2
/EN2
VCC
IOUT
CH_3
IN3
/EN3
RF_freq
RF
RS
RF_mag
GND
OSCEN
PWR_UP
Figure 1 - Functional Block Diagram
1
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Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.
ZL40518
Data Sheet
INR
IN2
GND
RF
IN3
/ENR
/EN2
/EN3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC_IN
VCC
IOUT
GND
RS
PWR_UP
OSCEN
VCC
Figure 2 - Pinout of 16 Pin SSO16 Package (Top View)
Description
The ZL40518 is a laser diode driver for high speed operation of a grounded laser diode. The driver consists of 3
controllable channels: a switchable, low noise, read channel and two switchable write channels. Write current
pulses are enabled with the application of a low signal on the /EN pins. A summed output of all channels is
available at the IOUT pin. Each channel can contribute up to 250 mA to the total output current of up to 300 mA. A
total read channel gain of 100 and write channels 2 and 3 with a gain of 250 and 150 respectively are provided
between each reference current input and output.
Laser mode hopping noise during read mode can be reduced by the use of an on-chip RF oscillator. The oscillator
frequency and swing can be set by two external resistors. The oscillator is enabled by a high signal on the OSCEN
pin and the entire device can be switched off by the application of a low signal on the PWR_UP pin.
Application Notes
Read and Write Channel Operation
The read channel is activated by applying a 'High' signal to the PWR_UP pin and applying a 'low' signal to /ENR. In
this mode, the fast write channels can be enabled by applying a 'Low signal to the respective pair of write enable
pins (/EN2) or (/EN3). The output currents of the three channels are summed together and output as a composite
signal at IOUT.
Voltage control of the channel reference inputs (INR, IN2 and IN3) can be achieved quite easily using an external
resistor R
ref
in series with the reference channel input to convert a given reference potential V
ref
to an input current,
I
in
:
I
in
=
V
ref
R
ref
+
R
in
,
where R
in
is the input impedance of the respective reference channel.
On-Chip RF Oscillator
An on-chip RF oscillator is enabled if OSCEN = 'High', and its output signal is added to the current output.The
oscillator amplitude is set by an external resistor from RS to GND. Its frequency is set by an external resistor RF to
GND. The oscillator signal is summed with the programmed Write and Read levels before amplification to the
output. The oscillator signal has zero DC level and +I_pk to -I_pk signal swing. Consequently, if the programmed
DC level from the Write and Read Channels is less than the PK level programmed for the Oscillator, the combined
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Zarlink Semiconductor Inc.
ZL40518
Data Sheet
signal will be clipped on the negative cycle of the signal. This will increase the harmonic content of the output signal
and reduce the pk to pk amplitude output.
Thermal Considerations
Package thermal resistance is 40° C/W under the EIA/JESD51-3 compliant PCB test board condition. Users should
ensure that the junction temperature does not exceed 150°C. Thermal resistance from junction to case and to
ambient is very much dependent on how the IC is mounted onto the board, on the PCB layout and on any heat
extraction arrangements. Power consumption and system ambient operating temperature limits should be noted
and careful thermal gradient calculations undertaken to ensure that the junction temperature never exceeds 150°C.
Electrical and Optical Pulse Response
Lfix = 3nH
Iout
En
2p
15
500
Lint
K
Lint
C_bypass
Vcc _A
K
Lfix = 3nH
OutA
C_out
17p
ZL40518 Model
Lint=5nH , BW = 460MHz, Rd=7, Q=j20/(15+7) =0.9
Lint=5nH, BW = 460MHz, Rd=3, Q=j20/(15+3) = 1.11
Lint=7nH, BW = 411MHz, Rd=7, Q=j18/(15+7) = 0.8
Lint=7nH, BW = 411MHz, Rd=3, Q=j18/(15+3) = 1.0
Cd
Rd
Vd
Figure 3 - Pulse Response Model
Figure 3 illustrates a simplified model of the typical ZL40518 and the application. The ZL40518 consist of an ideal
switched current source and an equivalent model of the ZL40518 output stage. The Electrical Model for the Laser
Diode is a Voltage source Vd (V_on) in series with the On Resistance Rd all in parallel with the Junction
Capacitance Cd. This simplified model approximately represents the Laser Diode Electrical load when operated
beyond the Laser Threshold. To a first approximation, the Optical output is proportional to the current flow in the
Resistor Rd.
The Laser Diode and the ZL40518 are connected together by interconnect tracks with the return current passing
through the supply decoupling bypass capacitor between ground and output Vcc. The ZL40518 will typically switch
the programmed output current in 400 ps and can be approximated to an ideal switch with a propagation delay of
Iout_on (1.2 nS). The electrical pulse response parameters, Trise, Tfall, Overshoot and Undershoot are determined
by the combined electrical network as illustrated in Figure 3.
For example, the Rise Time and Fall time for large current steps can be slew rate limited by the combined
interconnect and fixed interconnect inductance. The Fixed Inductance represents that associated with packaging
and minimum interconnect distance . The Interconnect Inductance is that associated with the additional tracking
between Laser Diode and the ZL40518 to accommodate application physical limitations.
For example, if a pulse of 260 mA amplitude (40 mA to 300 mA) is to be switched in a time of 1 ns with the Vd =
1.6 V, then the maximum volt drop across the interconnect inductance is approximately 3.5 V (maximum Vpin for
300 mA output) - 1.6 V (Vdiode) = 1.9 V. Consequently, L*di/dt < 1.9 V. Hence , L < 1.9/ (0.26A/1ns)
= 7.3 nH.
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Zarlink Semiconductor Inc.
ZL40518
Data Sheet
Small current step size Rise and Fall time will be determined by the Bandwidth of the combined network. This is
dominated by the Interconnect Inductance and the output Capacitance. Similarly, the overshoot and undershoot will
be determined by the Q of the network. This is a function of the Source Impedance from the ZL40518, the
Interconnect inductance and the Load impedance of the Laser Diode. Figure 3 includes example simplified
estimates of the Q and BW of the combined Laser Diode, ZL40518 and interconnect network for two different
interconnect inductance values (5 nH & 7 nH) and two different Diode On resistance (3 Ohm & 7 Ohm) . This
simple analysis illustrates the change in BW and Q of the network depending on these parameters. This in Turn
effects the Rise Time and Fall time and the Overshoot and Undershoot performance achieved in the application.
Specified Electrical Performance with 15 mm Interconnect and Zarlink ZLE40518 Evaluation Board
The specified performance in the table are results based on the electrical measurements and simulations across
full process corners using the Zarlink Evaluation Board using a 6.8 Ohm resistive load to ground. The track
interconnect between ZL40518 and the 6.8 Ohm Resistor is 15 mm long and uses a 2 mm wide track on single
sided FR4 board. The return path is via two 2 mm wide tracks spaced 0.25 mm either side of the track between
output and the 6.8 ohm resistor. The combined forward and return path forms a co planar transmission line with a
characteristic impedance of approximately 120 ohms. The tight coupled return paths carrying the return current
reduce the effective series inductance (Leff) which can be approximated to:-
L
eff
= 2 * Lint * (1 - K) + 2 * Lfix * (1 - K).
The ZLE40518 board has two positions for the Laser Diode at two different distances. (15 and 30 mm).
The measured value of L
eff
is 7 nH.
The estimated value of L
eff
= 2 * 8 (1 - 0.5) = 8 nH.
The actual pulse response achieved in an application is thus dependent on the application.
Application Layer Guide Lines
Minimize Interconnect Inductance by:-
a. Using Short Interconnect Distance
b. Use wide interconnect tracks
c. Keep the return path tightly coupled to the forward path
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Zarlink Semiconductor Inc.
ZL40518
ZLE40518 Interconnect
Data Sheet
Figure 4 - ZLE40518 Application Board Electrical Interconnect
Application Diagram
VCC
INR
IN2
ANALOG
INPUTS
GND
RF
IN3
/ENR
/EN2
/EN3
VCC_IN
1
2
3
4
5
4
7
8
16
15
14
13
12
11
10
9
VCC
IOUT
GND
RS
PWR_UP
OSCEN
VCC
LASER
DIODE
DIGITAL
INPUTS
Figure 5 - Evaluation Board Circuit
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