A29002/A290021 Series
256K X 8 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Features
5.0V
±
10% for read and write operations
Access times:
- 55/70/90/120/150 (max.)
Current:
- 20 mA typical active read current
- 30 mA typical program/erase current
- 1
µA
typical CMOS standby
Flexible sector architecture
-
16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX3 sectors
-
Any combination of sectors can be erased
-
Supports full chip erase
-
Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within that
sector
Top or bottom boot block configurations available
Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors
and verify the erased sectors
- Embedded Program algorithm automatically writes and
verifies bytes at specified addresses
Typical 100,000 program/erase cycles per sector
20-year data retention at 125°C
- Reliable operation for the life of the system
Compatible with JEDEC-standards
- Pinout and software compatible with single-power-
supply Flash memory standard
-
Superior inadvertent write protection
Data
Polling and toggle bits
-
Provides a software method of detecting completion of
program or erase operations
Erase Suspend/Erase Resume
-
Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then
resumes the erase operation
Hardware reset pin (
RESET
)
-
Hardware method to reset the device to reading array
data (not available on A290021)
Package options
-
32-pin P-DIP, PLCC, or TSOP (Forward type)
General Description
The A29002 is a 5.0 volt-only Flash memory organized as
262,144 bytes of 8 bits each. The A29002 offers the
RESET
function, but it is not available on A290021. The
256 Kbytes of data are further divided into seven sectors for
flexible sector erase capability. The 8 bits of data appear on
I/O
0
- I/O
7
while the addresses are input on A0 to A17. The
A29002 is offered in 32-pin PLCC, TSOP, and PDIP
packages. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply.
Additional 12.0 volt VPP is not required for in-system write or
erase operations. However, the A29002 can also be
programmed in standard EPROM programmers.
The A29002 has the first toggle bit, I/O
6
, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O
6
toggle bit, the
A29002 has a second toggle bit, I/O
2
, to indicate whether the
addressed sector is being selected for erase. The A29002
also offers the ability to program in the Erase Suspend
mode. The standard A29002 offers access times of 55, 70,
90, 120, and 150 ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention the
device has separate chip enable (
CE
), write enable (
WE
)
and output enable (
OE
) controls.
The device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The A29002 is entirely software command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed) before
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies proper
erase margin.
The host system can detect whether a program or erase
operation is complete by reading the I/O
7
(
Data
Polling) and
I/O
6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data contents
of other sectors. The A29002 is fully erased when shipped
from the factory.
(August, 2004, Version 1.3)
1
AMIC Technology, Corp.
A29002/A290021 Series
Absolute Maximum Ratings*
Ambient Operating Temperature . . . …... .-55°C to + 125°C
Storage Temperature . . . . . . . …. . . . …… -65°C to + 125°C
Ground to VCC . . . . . . . . . . . . . . …... . . …..….-2.0V to 7.0V
Output Voltage (Note 1) . . . .. . . … . ….... . …...-2.0V to 7.0V
A9,
OE
&
RESET
(Note 2) …… . . . . . . . . . . -2.0V to 12.5V
All other pins (Note 1) . . . . . . . . …… . . . . . . . -2.0V to 7.0V
Output Short Circuit Current (Note 3)…... . . . . . . . . . 200mA
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended periods
may affect device reliability.
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, inputs may undershoot VSS to -2.0V
for periods of up to 20ns. Maximum DC voltage on output
and I/O pins is VCC +0.5V. During voltage transitions,
outputs may overshoot to VCC +2.0V for periods up to
20ns.
2. Minimum DC input voltage on A9 pins is -0.5V. During
voltage transitions, A9,
OE
and
RESET
may overshoot
VSS to -2.0V for periods of up to 20ns. Maximum DC
input voltage on A9 and
OE
is +12.5V which may
overshoot to 13.5V for periods up to 20ns. (
RESET
is
N/A on A290021)
3. No more than one output is shorted at a time. Duration of
the short circuit should not be greater than one second.
Operating Ranges
Commercial (C) Devices
Ambient Temperature (T
A
) . . ….. . . . . . . . . . 0°C to +70°C
VCC Supply Voltages
VCC for
±
10% devices …. . . . . . . . . . . . . . +4.5V to +5.5V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Table 1. A29002/A290021 Device Bus Operations
Operation
CE
L
L
VCC
±
0.5 V
H
L
X
X
OE
L
H
X
X
H
X
X
WE
H
L
X
X
H
X
X
RESET
(N/A A290021)
H
H
VCC
±
0.5 V
VCC
±
0.5 V
H
L
V
ID
A0 – A17
I/O
0
- I/O
7
Read
Write
CMOS Standby
TTL Standby
Output Disable
Reset
Temporary Sector Unprotect (Note)
A
IN
A
IN
X
X
X
X
X
D
OUT
D
IN
High-Z
High-Z
High-Z
High-Z
X
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5V, X = Don't Care, D
IN
= Data In, D
OUT
= Data Out, A
IN
= Address In
Note: 1. See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.
2. This function is not available on A290021.
(August, 2004, Version 1.3)
4
AMIC Technology, Corp.
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