ZL10100
Single Chip Synthesized
Downconverter with IF Amplifier
Data Sheet
Features
•
Single chip synthesised downconverter forming a
complete double conversion tuner when
combined with the SL2100 or SL2101
Compatible with digital and analogue system
requirements
CTB contribution < -64 dBc, CXM contribution
< -62 dBc and spectral spread < -64 dBc
IF amplifier optimized to interface with standard
SAW filters
Extremely low phase noise balanced local
oscillator, with very low fundamental and
harmonic radiation
PLL frequency synthesizer designed for high
comparison frequencies and low phase noise
Available in 28 pin SSOP and MLP packages
Ordering Information
ZL10100/DDE
ZL10100/DDF
ZL10100/DDE1
ZL10100/DDF1
ZL10100/LDG1
ZL10100/LDF1
SSOP
SSOP
SSOP*
SSOP*
MLP*
MLP*
* Pb free
All codes Baked an Drypacked
-40°C to +85°C
April 2005
•
•
•
•
Tubes
Tape & Reel,
Tubes
Tape & Reel
Trays
Tape & Reel
•
•
Description
The ZL10100 is a fully integrated single chip mixer
oscillator with on-board low phase noise I2C bus
controlled PLL frequency synthesizer. It is intended
primarily as the down converter for application in
double conversion tuners and is compatible with HIIF
frequencies between 1 and 1.3 GHz and all standard
tuner IF output frequencies.
The device contains all elements necessary, with the
exception of local oscillator tuning network, loop filter
and crystal reference to fabricate a complete
synthesized block converter with IF amplifier,
compatible with digital and analogue requirements.
Applications
•
•
•
•
•
Double conversion tuners
Digital Terrestrial tuners
Cable Modems
Cable telephony
MATV
RF Input
RF InputB
IF Output
IF OutputB
LO
LOB
VCO
15 Bit
Programmable
Divider
Charge
Pump
fpd/
2
Pump
Drive
SDA
SCL
ADD
XTAL
XTALCAP
REF
OSC
I2C Bus
Interface
Fpd/2
Reference Divider
Fcomp
Port P0
Figure 1 - ZL10100 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved.
ZL10100
Pin Description
Data Sheet
IFOUTPUTB
Vee
VccRF
Vee
RFINPUTB
RFINPUT
Vee
Vee
VccD
Vee
SCL
SDA
XTAL
XTAL CAP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IFOUTPUT
Vee
VccIF
Vee
VccLO
LO
LOB
VccLO
Vee
ADD
Vee
Port P0
DRIVE
PUMP
Figure 2 - Pin Description SSOP Package
IFOUTPUTB
IFOUTPUT
VccRF
nc
RFINPUTB
nc
RFINPUT
nc
VccD
SCL
1
2
3
4
5
6
28 27 26 25 24 23 22
21
Pin 1 Ident
20
19
18
17
16
8
15
9 10 11 12 13 14
XTAL CAP
PUMP
XTAL
Port P0
Vee
DRIVE
VccIF
Vee
Vee
nc
nc
VccLO
LO
LOB
VccLO
ADD
nc
7
Vee to pad
under package
Figure 3 - Pin Description MLP Package
SDA
2
Zarlink Semiconductor Inc.
ZL10100
Quick Reference Data
All data applies with the following conditions unless otherwise stated;
a)
b)
Output load of 150
Ω,
differential
Input spectrum of 5 channels centred on 1220 MHz, each carrier @ 77 dBµV
Characteristic
RF input operating range
IF output operating range
Input noise figure, SSB
Conversion gain, diff to diff
CTB
CXM
Spectral spread
Local oscillator phase noise
SSB @ 10 kHz offset
SSB @ 100 kHz offset
Local oscillator phase noise floor
IF output impedance, differential
PLL phase noise at phase detector, 1 MHz comparison
frequency
1-1.3
30-60
9
24
< −66
< −63
< −70
c -93
c-115
-136
150
-152
Data Sheet
Units
GHz
MHz
dB
dB
dBc
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
Ω
dBc/Hz
3
Zarlink Semiconductor Inc.
ZL10100
1.0
Functional Description
Data Sheet
The ZL10100 is a bipolar, broadband wide dynamic range mixer oscillator with on-board I2C bus controlled PLL
frequency synthesizer, optimized for application as the down converter in double conversion tuner systems. It also
has application in any system where a wide dynamic range broadband synthesized frequency converter is required.
The ZL10100 is a single chip solution containing all necessary active circuitry and simply requires an external
tuneable resonant network for the local oscillator sustaining network. The pin assignment is contained in the block
diagram in Figure 1 and the Pin Description in Figure 2.
1.1
Converter Section
In normal application the HIIF input is interfaced through appropriate impedance matching to the device input. The
RF input preamplifier of the device is designed for low noise figure, within the operating region of 1 to 1.3 GHz and
for high intermodulation distortion intercept so offering good signal to noise plus composite distortion spurious
performance when loaded with a multi carrier system. The preamplifier also provides gain to the mixer section and
back isolation from the local oscillator section. The typical RF input impedance and matching network for matching
to a 1220 MHz HIIF filter, type B1603 are contained in Figures 3 and 4.
The output of the preamplifier is fed to the mixer section which is optimized for low radiation application. In this
stage the RF signal is mixed with the local oscillator frequency, which is generated by the on-board oscillator. The
oscillator block uses an external tuneable network and is optimized for low phase noise. The typical application is
shown in Figure 6, and the phase noise performance in Figure 7. This block interfaces direct with the internal PLL to
allow for frequency synthesis of the local oscillator.
The output of the mixer is internally coupled to a differential IF amplifier, which provides further gain and provides
for a 150
Ω,
differential output impedance and drive capability. The IF amplifier allows for IF frequencies between
30 and 60 MHz.
The typical IF output impedance is contained in Figure 8.
The typical key performance data at 5 V Vcc and 25 deg C ambient are shown in the Quick Reference Data section
on Page 2.
1.2
Local Oscillator
To maximize the local oscillator phase noise performance, the application circuit as in Figure 5 must be carefully
adhered to including the component type and manufacture where applicable, strip line dimension and board
material. Any deviation from these parameters may adversely affect phase noise characteristics and so will require
re-optimization.
1.3
PLL frequency Synthesizer
The PLL frequency synthesizer section contains all the elements necessary, with the exception of a reference
frequency source and loop filter to control the oscillator, so forming a complete PLL frequency synthesized source.
The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which
enables the generation of a loop with good phase noise performance.
The LO signal from the oscillator drives an internal preamplifier, which provides gain and reverse isolation from the
divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider. The
programmable divider is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is 4-bits,
and the M counter is 11 bits.
The output of the programmable divider is fed to the phase comparator where it is compared in both phase and
frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal
controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to
the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in Table 1.
4
Zarlink Semiconductor Inc.
ZL10100
Data Sheet
The typical application for the crystal oscillator is contained in Figure 9 which also demonstrates how a 4 MHz
reference signal can be coupled out to a further PLL frequency synthesizer, such as the upconverter section in a
double conversion tuner.
The output of the phase detector feeds a charge pump and loop amplifier, which when used with an external loop
filter and high voltage transistor, integrates the current pulses into the varactor line voltage, used for controlling the
oscillator.
The programmable divider output Fpd divided by two and the reference divider output Fcomp can be switched to
port P0 by programming the device into test mode. The test modes are described in Table 2.
2.0
Programming
The ZL10100 is controlled by an I2C data bus and is compatible with both standard and fast mode formats.
Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The device can
either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into
write mode if it is low, and read mode if it is high. Tables 3, 4 and 5 illustrate the format of the data. The device can
be programmed to respond to several addresses, which enables the use of more than one device in an I2C bus
system. Table 5 shows how the address is selected by applying a voltage to the 'ADD' input. When the device
receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during following
acknowledge periods after further data bytes are received. When the device is programmed into read mode, the
controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another
status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP
condition, which inhibits further reading.
2.1
Write Mode
With reference to Table 5, bytes 2 and 3 contain frequency information bits 214-20 inclusive. Byte 4 controls the
synthesizer reference divider ratio, see Table 1 and the charge pump setting, see Table 6. Byte 5 controls the test
modes, see Table 2 and the output port P0.
After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines
whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4. Having
interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively.
Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows
the same procedure, without re-addressing the device. This procedure continues until a STOP condition is
received. The STOP condition can be generated after any data byte, if however it occurs during a byte
transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only
accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP
condition.
2.2
Read Mode
When the device is in read mode, the status byte read from the device takes the form shown in Table 4.
Bit 1 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has dropped
below 3 V (at 25°C), e.g., when the device is initially turned ON. The POR is reset to '0' when the read sequence is
terminated by a STOP command. When POR is set high this indicates that the programmed information may have
been corrupted and the device reset to the power up condition.
Bit 2 (FL) indicates whether the synthesizer is phase locked, a logic '1' is present if the device is locked, and a logic
'0' if the device is unlocked.
5
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