Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
119, 165, & 209 BGA
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V or 2.5 V +10%/–10% core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-, 165-, or 209-Bump BGA package
-300 -275 -250 -225 -200 Unit
2.2 2.4 2.5 2.7 3.0 ns
3.3 3.6 4.0 4.4 5.0 ns
320
375
475
320
370
470
5.0
5.0
220
265
315
220
265
315
300
345
445
300
340
435
5.25
5.25
215
260
305
215
260
305
275
320
410
275
315
400
5.5
5.5
210
245
295
210
245
295
250
295
380
250
285
365
6.0
6.0
200
235
285
200
235
285
230
265
335
225
260
325
6.5
6.5
190
225
260
190
225
260
mA
mA
mA
mA
mA
mA
ns
ns
mA
mA
mA
mA
mA
mA
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
300 MHz–200 MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8162Z18A(B/D)/36A(B/D)/72A(C) may be
configured by the user to operate in Pipeline or Flow Through
mode. Operating as a pipelined synchronous device, in
addition to the rising-edge-triggered registers that capture input
signals, the device incorporates a rising edge triggered output
register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge-triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
The GS8162Z18A(B/D)/36A(B/D)/72A(C) is implemented
with GSI's high performance CMOS technology and is
available in a JEDEC-standard 119-bump (x18 & x36), 165-
bump (x18 & x36), or 209-bump (x72) BGA package.
Pipeline
3-1-1-1
2.5 V
1.8 V
Flow
Through
2-1-1-1
2.5 V
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
Curr
(x72)
Curr
(x18)
Curr
(x36)
Curr
(x72)
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
Curr
(x72)
Curr
(x18)
Curr
(x36)
Curr
(x72)
1.8 V
Functional Description
The GS8162Z18A(B/D)/36A(B/D)/72A(C) is a 16Mbit
Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT,
NtRAM, NoBL or other pipelined read/double late write or
flow through read/single late write SRAMs, allow utilization
of all available bus bandwidth by eliminating the need to insert
deselect cycles when the device is switched from read to write
cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
Rev: 1.02a 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/39
© 2001, Giga Semiconductor, Inc.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
GS8162Z72A 209-Bump BGA Pin Description
Symbol
A
0
, A
1
An
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
DQ
C1
–DQ
C9
DQ
D1
–DQ
D9
DQ
E1
–DQ
E9
DQ
F1
–DQ
F9
DQ
G1
–DQ
G9
DQ
H1
–DQ
H9
B
A
, B
B
, B
C
,B
D,
B
E
, B
F
,
B
G
,B
H
NC
CK
W
E
1,
E
3
E
2
G
ZZ
FT
LBO
MCH
MCL
PE
BW
ZQ
TMS
TDI
TDO
TCK
V
DD
V
SS
V
DDQ
I
I
I
I
I
O
I
I
I
I
Type
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
I/O
Data Input and Output pins
I
—
I
I
I
I
I
I
I
I
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D,
DQ
E
,
DQ
F
, DQ
G
, DQ
H
I/Os; active low
No Connect
Clock Input Signal; active high
Write Enable. Writes all enabled bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Must Connect High
Must Connect Low
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
Byte Enable; active low
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.02a 9/2002
3/39
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
