October 2006
rev 1.3
Low Frequency EMI Reduction
Features
•
•
FCC approved method of EMI attenuation
Generates a low EMI spread spectrum and a non
spread reference signal of the input clock
frequency
•
•
•
•
•
•
•
Optimized for input frequency range from
20 to 32MHz
Internal loop filter minimizes external components
and board space
Two selectable spread ranges
3.3V Operating Voltage
Ultra low power CMOS design: 5.50 mA @3.3V
Supports notebook VGA and other LCD timing
controller applications
Available in 8-pin SOIC and TSSOP
P2560B
circuit board layers and shielding traditionally required to
pass EMI regulations.
The P2560B modulates the output of a single PLL in order to
spread the bandwidth of a synthesized clock, thereby
decreasing the peak amplitudes of its harmonics.
This results in significantly lower system EMI compared to
the typical narrow band signal produced by oscillators and
most clock generators. Lowering EMI by increasing a signal’s
bandwidth is called spread spectrum clock generation.
The P2560B uses the most efficient and optimized
modulation profile approved by the FCC and is implemented
by using a proprietary all-digital method.
Applications
Product Description
The P2560B is a versatile spread spectrum frequency
modulator designed specifically for a wide range of clock
frequencies. It reduces electromagnetic interference (EMI) at
the clock source allowing system-wide reduction of EMI of
downstream clock and data dependent signals. It allows
significant system cost savings by reducing the number of
The P2560B is targeted toward the notebook VGA chip and
other displays using an LVDS interface, PC peripheral
devices and embedded systems.
Block Diagram
VDD
XIN /CLKIN
Crystal
Oscillator
XOUT
Frequency
Divider
Feedback
Divider
Modulation
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
October 2006
rev 1.3
Pin Configuration
XIN / CLKIN
VDD
VSS
ModOUT
1
2
3
4
8
7
6
5
XOUT
NC
NC
NC
P2560B
P2560B
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin Name
XIN / CLKIN
VDD
VSS
ModOUT
NC
NC
NC
XOUT
Type
I
P
P
O
-
-
-
O
Description
Crystal Connection or external frequency input. This pin has dual functions.
It can be connected to either an external crystal or an external reference
clock
Power Supply for the entire chip.
Ground to entire chip.
Spread spectrum low EMI output.
No Connect
No Connect
No Connect
Crystal Connection. If using an external reference, this pin must be left
unconnected.
Spread Range Selection, VDD = 3.3 V
CLKIN frequency
20 MHz
25 MHz
27 MHz
30 MHz
32 MHz
Spreading range
±1.16%
±1.13%
±1.11%
±1.10%
±1.10%
Modulation rate
(CLKIN/10) * 20.83 kHz
Low Frequency EMI Reduction
Notice: The information in this document is subject to change without notice.
2 of 8
October 2006
rev 1.3
Schematic for Notebook VGA Application
27 MHz
27pF
P2560B
27pF
VDD
FB : Optional ferrite bead
FB
0.1uF
GND
1
2
3
4
CLKIN/XIN
VDD
VSS
ModOUT
XOUT
NC
NC
NC
8
7
6
5
P2560B
Absolute Maximum Ratings
Symbol
V
DD
, V
IN
T
STG
T
A
T
s
T
J
T
DV
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD 22- A114-B)
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +4.6
-65 to +125
-40 to +85
260
150
2
Unit
V
°C
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Low Frequency EMI Reduction
Notice: The information in this document is subject to change without notice.
3 of 8
October 2006
rev 1.3
DC Electrical Characteristics
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
DD
I
CC
V
DD
t
ON
Z
OUT
Input Low Voltage
Input High Voltage
Input Low current
Input High current
XOUT Output low current
XOUT Output high current
Output Low Voltage
Output High Voltage
Static supply current
Dynamic supply current
Operating Voltage
Power up time (first locked clock cycle after power up)
Clock Output impedance
V
XOL
at 0.4V, V
DD
= 3.3V
V
XOH
at 2.5V, V
DD
= 3.3V
V
DD
= 3.3V, I
OH
= 20mA
V
DD
= 3.3V, I
OH
= 20mA
CLKIN / XIN pulled LOW
3.3V and 10pF loading
P2560B
Parameter
Min
VSS – 0.3
2.0
-60.0
-
-
-
-
2.5
-
3.2
3.0
-
-
Typ
-
-
-
-
3
3
-
-
0.6
-
3.3
0.18
50
Max
0.8
VDD + 0.3
-35
35
-
-
0.4
-
-
7.0
3.6
-
-
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
V
mS
Ω
AC Electrical Characteristics
Symbol
f
IN
f
OUT
t
LH1
t
HL1
t
JC
t
D
Input Frequency
Output Frequency
Output Rise time
Output Fall time
Measured from 0.8V to 2.0V
Measured from 2.0V to 0.8V
Parameter
Min
20
20
0.7
0.6
-
45
Typ
-
-
0.9
0.8
-
50
Max
32
32
1.1
1.0
360
55
Unit
MHz
MHz
nS
nS
pS
%
Jitter (Cycle to cycle)
Output Duty cycle
Note: 1. t
LH
and t
HL
are measured into a capacitive load of 15pF
Low Frequency EMI Reduction
Notice: The information in this document is subject to change without notice.
4 of 8
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