4 Megabit CMOS EEPROM
DPE128X32V
DESCRIPTION:
The DPE128X32V is a high-performance Electrically Erasable
and Programmable Read Only Memory (EEPROM) module
and may be organized as 128K X 32, 256K X 16 or 512K X 8.
The module is built with four low-power CMOS 128K X 8
EEPROMs. The four chip enables are used for individual
BWDW* selection. The DPE128X32V is ideally suited for
those computer systems having 16-bit or 32-bit architectures.
The DPE128X32V contains a 128-BWDW page register to
allow writing of up to 128 BWDWs simultaneously. During
a write cycle, the address and 1 to 128 BWDWs of data are
internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the
module will automatically write the latched data using an
internal control timer. The end of a write cycle can be
detected by DATA Polling of the most significant data bit in
each byte. Once the end of a write cycle has been detected,
a new access for a read or write can begin.
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
Fast Access Times: 120, 150, 200, 250ns
Organizations Available:
128K X 32, 256K X 16 or 512K X 8
Automatic Page Write Operation
Internal Address and Data Latches
Internal Control Timer
Fast Write Cycle Times
Page Write Cycle Time: 10ms maximum
1 to 128 BWDW* Page Write Operation
DATA Polling for END of Write Detection
High Reliability CMOS Technology
Endurance: 10
4
Cycles
Data Retention: 10 years
Single +5V Power Supply,
±10%
Tolerance
CMOS and TTL Compatible Inputs and Outputs
Available with All Semiconductor Components
used to Construct the Module Compliant to
MIL-STD-883; Class B
66-Pin PGA (Grid Array) Package
Same Package as other Versapac Versions
(SRAMs, EPROMs, and Mixed)
PIN NAMES
A0 - A16
I/O0 - I/O31
CE0 - CE3
WE0 - WE3
OE
V
DD
V
SS
N.C.
Address Inputs
Data In/Out
Chip Enables
Write Enables
Output Enable
Power (+5V)
Ground
No Connect
* Byte, Word or Double Word (BWDW).
PIN-OUT DIAGRAM
30A014-25
REV. D
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
DPE128X32V
RECOMMENDED OPERATING RANGE
Symbol
Characteristic
Min. Typ.
V
DD
Supply Voltage
4.5 5.0
V
IH
Input HIGH Voltage 2.0
V
IL
Input LOW Voltage
C
0 +25
Operating
T
A
I
-40 +25
Temperature
M/B -55 +25
Max.
5.5
0.8
+70
+85
+125
1
Dense-Pac Microsystems, Inc.
TRUTH TABLE
Unit
V
V
V
o
C
Mode
Standby
Read
Write
Write Inhibit
Write Inhibit
L = LOW
CE
H
L
L
X
X
H = HIGH
OE
X
L
H
L
X
WE
X
H
L
X
H
I/I Pin
HIGH-Z
D
OUT
D
IN
HIGH-Z
HIGH-Z
X = Don’t Care
ABSOLUTE MAXIMUM RATINGS
Symbol
T
STG
T
BIAS
V
DD
V
I/O
Parameter
Storage Temperature
Temperature Under Bias
Supply Voltage
2
Input/Output Voltage
2
1
Value
-65 to +150
-65 to +135
-0.6 to +6.25
-0.6 to +6.25
Unit
°C
°C
°C
V
CAPACITANCE
3
: T
A
= 25
°
C, F = 1.0MHz
Symbol
C
CE
C
ADR
C
WE
C
OE
C
I/O
Parameter
Chip Enable
Address Input
Write Enable
Output Enable
Data Input/Output
Max.
30
70
70
70
30
Unit
Condition
pF
V
IN
= 0V
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
* Transition between 0.8V and 2.2V.
0V to 3.0V
5ns*
1.5V
Figure 1. Output Load
** Including Probe and Jig Capacitance.
+5V
1.8KΩ
D
OUT
C
L
**
1.3KΩ
OUTPUT LOAD
Load
1
2
C
L
100pF
5pF
Parameters Measured
except t
DF
t
DF
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
VIL
VIH
V
OL
V
OH
Characteristics
Input
Leakage Current
Output
Leakage Current
Operating Supply
Current
V
DD
Standby
Current (TTL)
V
DD
Standby
Current (CMOS)
Input Voltage Low
Input Voltacge High
Output Voltage Low
Output Voltage High
Test Conditions
V
IN
= V
DD
Max.
V
OUT
= V
DD
Max.
CE = OE = V
IL
,
all I/O = 0mA, f = 5MHz
CE = V
IH
CE = V
DD
-0.3Vdc
2.0
I
OUT
= 2.1mA
I
OUT
= -400µA
0.45
2.4
2.4
X32
Min.
Max.
Min.
X16
Max.
Min.
X8
Max.
Unit
µA
µA
mA
mA
mA
V
V
V
V
-40
-10
+40
+10
320
12
1.2
0.8
-40
-20
+40
+20
170
12
1.2
0.8
-40
-40
+40
+40
90
12
1.2
0.8
2.0
0.45
2.0
0.45
2.4
2
30A014-25
REV. D
Dense-Pac Microsystems, Inc.
DPE128X32V
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
Over operating ranges
No.
1
2
3
4
5
6
Symbol
t
RC
t
CE
t
ACC
t
OE
t
DF
t
OH
Parameter
Read Cycle Time
Chip Enable to Output Valid
Address Access Time
Output Enable Access Time
Chip Enable or Output Enable to Output Float
3
Output Hold from Chip Enable, Output Enable,
or Address, Whichever Occurs First
120ns
Min. Max.
150ns
Min. Max.
200ns
Min.
250ns
250
Max. Min. Max.
Unit
ns
ns
ns
ns
ns
ns
120
120
120
50
50
0
150
150
150
55
55
0
200
200
200
55
55
0
250
250
55
55
0
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE:
Over operating ranges
5, 6
No.
7
8
9
10
11
12
13
14
15
16
17
18
19
Symbol
t
WC
t
AS
t
AH
t
CS
t
CH
t
WP
t
DS
t
DH
t
OES
t
OEH
t
WPH
t
BLC
t
WR
Parameter
Write Cycle Time
Address Set-up Time *
Address Hold Time
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
Data Hold Time
Output Enable Set-up Time
Output Enable Hold Time
Write Pulse Width High
Byte Load Cycle Time
Write Recovery Time
Min.
0
50
0
0
100
50
0
0
0
50
150
0
Max.
10
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
* Valid for both Read and Write Cycles.
READ CYCLE
ADDRESS
CE
OE
DATA I/O
30A014-25
REV. D
3
DPE128X32V
Dense-Pac Microsystems, Inc.
WRITE CYCLE 1:
WE Controlled.
OE
ADDRESS
CE
WE
DATA IN
WRITE CYCLE 2:
CE Controlled.
OE
ADDRESS
WE
CE
DATA IN
WAVEFORM KEY
Data Valid
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
4
30A014-25
REV. D
Dense-Pac Microsystems, Inc.
PAGE MODE WRITE WAVEFORM
OE
DPE128X32V
CE
WE
A0 - A6
DATA
DATA POLLING WAVEFORM
WE
CE
OE
I/O7, I/O15,
I/O23 and/or
I/O31
A0 - A6
DEVICE OPERATION
READ:
The DPE12832V is accessed like a Static RAM. When CE
and OE are low and WE is high, the data stored at the memory
location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state whenever CE or
OE is high. This dual line control gives designers flexibility in
preventing bus contention.
WRITE:
A low pulse on the WE or CE input with CE or WE low
(respectively) and OE high initiates a write cycle. The address is
latched on the falling edge of CE or WE. Once a **BWDW Write
has been started it will automatically time itself to completion.
PAGE WRITE:
The page write operation of the DPE12832V
allows 1 to 128 BWDWs of data to be loaded into the device and
then simultaneously written during the internal programming
period. After the first data BWDW has been loaded into the device,
successive BWDWs may be loaded in the same manner. Each new
BWDW to written must have its high to low transition on WE (or
CE) within 150µs of the low to high transition of WE (or CE) of the
preceding BWDW. If a high to low transition is not detected within
150µs of the last low to high transition, the load period will end
30A014-25
REV. D
and the internal programming period will start. A7 to A16 specify
the page address. The page address must be valid during each high
to low transition of WE (or CE). A0 to A6 are used to specify which
BWDW within the page are to be written. The BWDWs may
loaded in any order and may be changed within the same load
period. Only BWDWs which are specified for writing will be
written; unnecessary cycling of other BWDWs within the page does
not occur.
DATA POLLING:
Write cycles typically are completed in less
time than the maximum write cycle time of 10ms. To determine
when the write is completed, a method called DATA Polling is
utilized. If a read is performed on the address of the last BWDW
written to the DPE12832V while a write cycle is in progress, the
one’s compliment of data most significant bit (I/O7, I/O15, I/O23
and I/O31) will appear on the output. When the write is completed,
a read from the last address written will return valid data. A DATA
Polling may begin at any time during the Write Cycle.
** Byte, Word, or Double Word.
5
京公网安备 11010802033920号
EEWORLD
