7-bit programmable ‘A’ counter and the necessary control and
latch circuitry for accepting and latching the input data.
Data is presented as eight 4-bit words read from an external
memory, with the necessary timing signals generated internally.
It is intended to be used in conjunction with a two-modulus
prescaler such as the SP8710 series to produce a universal
binary coded synthesiser.
The NJ8820 is available in Plastic DIL (DP) and Miniature
Plastic DIL (MP) packages, both with operating temperature
range of
230°C
to
170°C.
The NJ8820MA is available only in
Ceramic DIL package with operating temperature range of
240°C
to
185°C.
PDA
PDB
LD
F
IN
V
SS
V
DD
OSC IN
OSC OUT
D0
D1
1
2
3
4
5
20
19
18
17
16
CH
RB
MC
DS2
DS1
DS0
PE
ME
D3
D2
NJ8820
6
7
8
9
10
15
14
13
12
11
DP20, MP20,
DG20
FEATURES
s
s
s
s
Low Power Consumption
Direct Interface to ROM or PROM
High Performance Sample and Hold Phase Detector
>10MHz Input Frequency
Fig.1 Pin connections - top view
ABSOLUTE MAXIMUM RATINGS
20·5V
to 7V
Supply voltage, V
DD
2V
SS
Input voltage
7V
Open drain outputs, pins 3 and 13
V
SS
20·3V
to V
DD
10·3V
All other pins
Storage temperature
265°C
to
1150°C
(DG package, NJ8820MA)
255°C
to
1125°C
Storage temperature
(DP and MP packages, NJ8820)
ORDERING INFORMATION
NJ8820 BA DP
Plastic DIL Package
NJ8820 BA MP
Miniature Plastic DIL Package
NJ8820 MA DG
Ceramic DIL Package
MEMORY ENABLE
(ME)
13
PROGRAM
ENABLE (PE)
14
PULSE
DETECT
SEQUENCE
COUNTER
DATA SELECT
OUTPUTS
DS0 DS1 DS2
15
16
17
TO
INTERNAL
LATCHES
RB
19
CH
20
OSC IN
OSC OUT
7
8
REFERENCE COUNTER
(11BITS)
42
f
r
SAMPLE/HOLD
PHASE
DETECTOR
FREQUENCY/
PHASE
DETECTOR
1
PDA
LATCH 6 LATCH 7 LATCH 8
2
DATA
INPUTS
D0
D1
D2
D3
9
10
11
12
PDB
3
V
SS
LOCK DETECT (LD)
LATCH 4 LATCH 5
LATCH 1 LATCH 2 LATCH 3
F
IN
4
‘A’ COUNTER
(7 BITS)
‘M’ COUNTER
(10 BITS)
f
v
V
DD
V
SS
6
CONTROL LOGIC
5
18
MODULUS
CONTROL
OUTPUT (MC)
Fig.2 Block diagram
NJ8820
ELECTRICAL CHARACTERISTICS AT V
DD
= 5V
Test conditions unless otherwise stated:
V
DD
–V
SS
=5V
±0·5V.
Temperature range NJ8820 BA: –30°C to +70°C; NJ8820 MA: –40°C to +85°C
DC Characteristics
Characteristic
Min.
Supply current
OUTPUT LEVELS
Memory Enable Output (ME)
Low level
Open drain pull-up voltage
Data Select Outputs (DS0-DS2)
High level
Low level
Modulus Control Output (MC)
High level
Low level
Lock Detect Output (LD)
Low level
Open drain pull-up voltage
PDB Output
High level
Low level
3-state leakage current
INPUT LEVELS
Data Inputs (D0-D3)
High level
Low level
Program Enable Input (PE)
Trigger level
Value
Typ.
3·5
0·7
Max.
5·5
1·5
mA
mA
Units
Conditions
f
osc
, f
F
IN
= 10MHz
f
osc
, f
F
IN
= 1·0MHz
0 to 5V
square
wave
0·4
7
4·6
0·4
4·6
0·4
0·4
7
4·6
0·4
60·1
V
V
V
V
V
V
V
V
V
V
µA
I
SINK
= 4mA
I
SOURCE
= 1mA
I
SINK
= 2mA
I
SOURCE
= 1mA
I
SINK
= 1mA
I
SINK
= 4mA
I
SOURCE
= 5mA
I
SINK
= 5mA
4·25
0·75
V
BIAS
6100mV
V
V
V
TTL compatible
See note 1
V
BIAS
= self-bias point of PE
(nominally V
DD
/2)
AC Characteristics
Characteristic
Min.
F
IN
and OSC IN input level
Max. operating frequency, f
F
IN
and f
osc
Propagation delay, clock to MC
PE pulse length, t
W
Data set-up time, t
DS
Data hold time, t
DH
Digital phase detector propagation delay
Gain programming resistor, RB
Hold capacitor, CH
Output resistance, PDA
Digital phase detector gain
Power supply rise time
200
10·6
30
5
1
10
500
5
1
5
0·4
100
50
Value
Typ.
Max.
Units
Conditions
mVRMS 10MHz AC-coupled sinewave
MHz
Input squarewave V
DD
to V
SS
,
See note 5.
See note 2.
ns
Pulse to V
SS
or V
DD
.
µs
µs
ns
ns
kΩ
See note 3.
nF
kΩ
V/Rad
10% to 90%, see note 4.
µs
NOTES
1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant
to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs, typically.
4. To ensure correct operation of power-on programming.
5. Operation at up to 15MHz is possible with a full logic swing but is not guaranteed.
2
NJ8820
PIN DESCRIPTIONS
Pin no.
1
Name
PDA
Description
Analog output from the sample and hold phase comparator for use as a ‘fine’ error signal. Output at
(V
DD
2V
SS
)/2 when the system is in lock. Voltage increases as f
v
phase lead increases; voltage
decreases as f
r
phase lead increases. Output is linear over only a narrow phase window, determined
by gain (programmed by RB).
Three-state output from the phase/frequency detector for use as a ‘coarse’ error signal.
f
v
.
f
r
or f
v
leading: positive pulses with respect to the bias point V
BIAS
f
v
,
f
r
or f
r
leading: negative pulses with respect to the bias point V
BIAS
f
v
= f
r
and phase error within PDA window: high impedance.
An open-drain lock detect output at low level when phase error is within PDA window (in lock); high
impedance at all other times.
The input to the main counters, normally driven from a prescaler, which may be AC-coupled or, when
a full logic swing is available, may be DC-coupled.
Negative supply (ground).
Positive supply.
2
PDB
3
4
5
6
7, 8
LD
F
IN
V
SS
V
DD
OSC IN/ These pins form an on-chip reference oscillator when a series resonant crystal is connected across
OSC OUT them. Capacitors of appropriate value are also required between each end of the crystal and ground
to provide the necessary additional phase shift. An external reference signal may, alternatively, be
applied to OSC IN. This may be a low-level signal, AC-coupled, or if a full logic swing is available it may
be DC-coupled. The program range of the reference counter is 3 to 2047, with the division ratio being
twice the programmed number.
D0-D3
ME
PE
DS0-DS2
MC
Information on these inputs is transferred to the internal data latches during the appropriate data read
time slot. D3 is MSB, D0 is LSB.
An open drain output for use in controlling the power supply to an external ROM or PROM. ME is low
during the data read period and high impedance at other times.
A positive or negative pulse or edge AC-coupled into this pin initiates the single-shot data read
procedure. Grounding this pin repeats the data read procedure in a cyclic manner.
Internally generated three-state data select outputs, which may be used to address external memory.
Modulus control output for controlling an external dual-modulus prescaler. MC will be low at the beginning
of a count cycle and will remain low until the ‘A’ counter completes its cycle. MC then goes high and
remains high until the ‘M’ counter completes its cycle, at which point both ‘A’ and ‘M’ counters are reset.
This gives a total division ratio of
MP
1
A,
where
P
and
P
11
represent the dual-modulus prescaler
values. The program range of the ‘A’ counter is 0-127 and therefore can control prescalers with a
division ratio up to and including
4128/129.
The programming range of the ‘M’ counter is 8-1023
and, for correct operation,
M
>
A.
Where every possible channel is required, the minimum total division
ratio should be
P
2
2
P.
An external sample and hold phase comparator gain programming resistor should be connected
between this pin and V
SS
.
An external hold capacitor should be connected between this pin and V
SS
.
8
V
DD
= 5V
OSC IN, F
IN
= 0V TO 5V SQUARE WAVE
7
SUPPLY CURRENT (mA)
6
5
10MHz
4
1MHz
3
2
TOTAL SUPPLY CURRENT IS
THE SUM OF THAT DUE TO F
IN
AND OSC IN
1
2
3
4
5
6
7
INPUT FREQUENCY (MHz)
8
9
10
1
V
DD
= 5V
F
IN
= LOW FREQUENCY
0V TO 5V SQUARE WAVE
9,10, 11, 12
13
14
15, 16, 17
18
19
20
2·0
RB
CH
SUPPLY CURRENT (mA)
1·5
OSC IN
1·0
F
IN
0·5
0·2
0·4
0·6
0·8
1·0
1·2
INPUT LEVEL (V RMS)
1·4
1·6
Fig. 3 Typical supply current v. input frequency
Fig. 4 Typical supply current v. input level, OSC IN
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