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PDM31096SA20SOITY

Description
Standard SRAM, 512KX8, 20ns, CMOS, PDSO36
Categorystorage    storage   
File Size169KB,7 Pages
ManufacturerParadigm Technology Inc
Download Datasheet Parametric View All

PDM31096SA20SOITY Overview

Standard SRAM, 512KX8, 20ns, CMOS, PDSO36

PDM31096SA20SOITY Parametric

Parameter NameAttribute value
MakerParadigm Technology Inc
package instruction,
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time20 ns
JESD-30 codeR-PDSO-J36
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of ports1
Number of terminals36
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize512KX8
Output characteristics3-STATE
ExportableYES
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formJ BEND
Terminal locationDUAL
PRELIMINARY
PDM31096
4 Megabit 3.3V Static RAM
512K x 8-Bit
Features
n
Description
The PDM31096 is a high-performance CMOS static
RAM organized as 524,288 x 8 bits. Writing is
accomplished when the write enable (WE) and chip
enable CE inputs are both LOW. Reading is
accomplished when WE remains HIGH and CE and
OE are both LOW.
The PDM31096 operates from a single +3.3V power
supply and all the inputs and outputs are fully TTL-
compatible.
The PDM31096 is available in a 36-pin 400-mil plas-
tic SOJ package and a 44-pin plastic TSOP (II)
package.
1
2
3
4
5
6
High-speed access times
Com’l: 8, 10, 12, 15, and 20 ns
Ind’l.: 12, 15 and 20 ns
Low power operation
- PDM31096SA
Active: 300 mA (Max)
Standby: 25mW
Single +3.3V (±0.3V) power supply
TTL-compatible inputs and outputs
Packages
Plastic SOJ (400 mil) - SO
Plastic TSOP (II) - T
n
n
n
n
Functional Block Diagram
A
0
A
18
7
Decoder
Memory
Matrix
8
9
10
Addresses
I/O
0
I/O
7
• • • • •
Input
Data
Control
Column I/O
11
12
1
CE
WE
OE
Rev. 2.4 - 5/27/98
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