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IDT10480S15D

Description
Standard SRAM, 16KX1, 15ns, BICMOS, CDIP20, 0.300 INCH, CERDIP-20
Categorystorage    storage   
File Size66KB,7 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT10480S15D Overview

Standard SRAM, 16KX1, 15ns, BICMOS, CDIP20, 0.300 INCH, CERDIP-20

IDT10480S15D Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeDIP
package instruction0.300 INCH, CERDIP-20
Contacts20
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time15 ns
I/O typeSEPARATE
JESD-30 codeR-GDIP-T20
JESD-609 codee0
length25.3365 mm
memory density16384 bit
Memory IC TypeSTANDARD SRAM
memory width1
Negative supply voltage rating-5.2 V
Number of functions1
Number of terminals20
word count16384 words
character code16000
Operating modeASYNCHRONOUS
Maximum operating temperature75 °C
Minimum operating temperature
organize16KX1
Output characteristicsOPEN-EMITTER
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Encapsulate equivalent codeDIP20,.3
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply-5.2 V
Certification statusNot Qualified
Maximum seat height5.08 mm
surface mountNO
technologyBICMOS
Temperature levelCOMMERCIAL EXTENDED
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
®
HIGH-SPEED BiCMOS
ECL STATIC RAM
16K (16K x 1-BIT) SRAM
Integrated Device Technology, Inc.
PRELIMINARY
IDT10480
IDT100480
IDT101480
FEATURES:
• 16,384 x 1-bit organization
• Address access time: 3/3.5/4/5/7/8/10/12/15 ns
• Low power dissipation: 1000mW (typ.)
• Guaranteed Output Hold time
• Fully compatible with ECL logic levels
• Separate data input and output
• JEDEC standard through-hole package
• Guaranteed-performance die available for MCMs/hybrids
DESCRIPTION:
The IDT10480, IDT100480 and IDT101480 are 16,384-bit
high-speed BiCMOS ECL static random access memories
organized as 16K x 1, with separate data input and output. All
I/Os are fully compatible with ECL levels.
These devices are part of a family of asynchronous one-bit-
wide ECL SRAMs. The device has been configured to follow
the standard ECL SRAM JEDEC pinout. Because they are
manufactured in BiCMOS technology, power dissipation is
greatly reduced over equivalent bipolar devices.
The fast access time and guaranteed Output Hold time
allow greater margin for system timing variation. DataIN setup
time specified with respect to the trailing edge of Write Pulse
eases write timing allowing balanced Read and Write cycle
times.
FUNCTIONAL BLOCK DIAGRAM
A
0
V
CC
DECODER
16,384-BIT
MEMORY
ARRAY
V
EE
A
13
D
0
SENSE AMPS
AND READ/WRITE
CONTROL
Q
0
WE
CS
2759 drw 01
The IDT logo is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1992
Integrated Device Technology, Inc.
SEPTEMBER 1992
DSC-8023/2
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