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MSM8129JXM-025

Description
Standard SRAM, 128KX8, 25ns, CMOS, CQCC32, CERAMIC, LCC-32
Categorystorage    storage   
File Size465KB,8 Pages
ManufacturerAPTA Group Inc
Download Datasheet Parametric View All

MSM8129JXM-025 Overview

Standard SRAM, 128KX8, 25ns, CMOS, CQCC32, CERAMIC, LCC-32

MSM8129JXM-025 Parametric

Parameter NameAttribute value
MakerAPTA Group Inc
Parts packaging codeQFJ
package instructionQCCJ, LDCC32,.5X.6
Contacts32
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Maximum access time25 ns
I/O typeCOMMON
JESD-30 codeR-CQCC-J32
length14.03 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX8
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC32,.5X.6
Package shapeRECTANGULAR
Package formCHIP CARRIER
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Maximum standby current0.03 A
Minimum standby current4.5 V
Maximum slew rate0.17 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
width11.5 mm
hmp
Description
128K x 8 SRAM
MSM8129 - 020/025/35
Issue 3 : September 2002
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
128K x 8 CMOS Fast Static RAM
Features
Fast Access Times of 020/025/35 ns
High Density Packages.
Single CS pinout variant
Operating Power 940 mW (max)
Standby Power
165 mW (max)
Completely Static Operation
May be processed in accordance with
MIL-STD-883C
The MSM8129 is a 1Mbit monolithic SRAM organised
as 128K x 8 with access times from 20ns to 35ns
available. The device is available in two 32 pin ceramic
surface mount packages. The device is directly TTL
compatible.
All versions can be screened in accordance with MIL-
STD-883C.
GND
Block Diagram
CLK Gen.
Pre-Charge Circuit
Pin Definition
D6
D5
D4
D3
D2
A0
A1
A2
A3
A4
A5
A6
A7
A12
Row Select
20 19 18 17 16 15 14
Memory Arrays
512 Rows
256 x 8
D1 ~ D8
Data
Cont.
I/O Circuit
Column Select
CLK
Gen.
A8
A9
A10
A11
CS2
/CS1
A16
A15
A14
A13
D7
CS1
A10
OE
A11
A9
A8
A13
WE
21
22
23
24
25
26
27
28
29
D1
JX / WX
13
12
11
10
9
8
7
6
5
D0
A0
A1
A2
A3
A4
A5
A6
A7
1
30 31 32
2 3 4
A15
NC
A16
/OE
Package Details
Pin Count
32
32
Descripion
JLCC Package
LCC Package
Package Type
JX
WX
Pin Functions
A0~A16
Address Inputs
D0~7
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
Power (+5V)
V
CC
GND
Ground
VCC
A14
A12
NC
/WE
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