MBM29LV017
-80/-90/-12
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices
and Fujitsu. Although the document is marked with the name of the company that originally developed the specifi-
cation, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that
have been made are the result of normal datasheet improvement and are noted in the document revision summary,
where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision sum-
mary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these prod-
ucts, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.
Publication Number
26829
Revision
A
Amendment
0
Issue Date
October 25, 2002
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20857-5E
FLASH MEMORY
CMOS
16M (2M
×
8) BIT
MBM29LV017
-80/-90/-12
s
FEATURES
• Address specification is not necessary during command sequence
• Single 3.0 V read, program and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
• Compatible with JEDEC-standard world-wide pinouts
40-pin TSOP (1) (Package suffix: PTN-Normal Bend Type, PTR-Reversed Bend Type)
48-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
80 ns maximum access time
• Sector erase architecture
Uniform sectors of 64K bytes each
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Embedded Erase
TM
* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded program
TM
* Algorithms
Automatically programs and verifies data at specified address
(Continued)
s
PRODUCT LINE UP
Part No.
V
CC
= 3.3 V
Ordering Part No.
V
CC
= 3.0 V
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
+0.3 V
–0.3 V
+0.6 V
–0.3 V
MBM29LV017
-80
—
80
80
30
—
-90
90
90
35
—
-12
120
120
50
MBM29LV017
-80/-90/-12
(Continued)
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switches themselves to low power mode
• Low V
CC
write inhibit
≤
2.5 V
• Hardware RESET pin
Resets internal state machine to the read mode
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector protection
Hardware method disables any combination of sectors from program or erase operations
• Sector Protection set function by Extended sector protect command
• Temporary sector unprotection
Temporary sector unprotection via the RESET pin
• In accordance with CFI (Common Flash Memory Interface)
*: Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
s
PACKAGES
40-pin plastic TSOP (1)
Marking Side
40-pin plastic TSOP (1)
Marking Side
(FPT-40P-M06)
(FPT-40P-M07)
48-ball plastic FBGA
(BGA-48P-M03)
(BGA-48P-M13)
2
MBM29LV017
-80/-90/-12
s
GENERAL DESCRIPTION
The MBM29LV017 is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each. The 2M bytes
of data is divided into 32 sectors of 64K bytes of flexible erase capability. The 8 bits of data will appear on DQ
0
to DQ
7
. The MBM29LV017 is offered in a 40-pin TSOP (1), 48-ball FBGA packages. The device is designed to
be programmed in-system with the standard system 3.0 V V
CC
supply. 12.0 V V
PP
and 5.0 V V
CC
are not required
for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29LV017 offers access times of 80 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29LV017 is pin and command set compatible with JEDEC standard E
2
PROMs. Commands are written
to the command register using standard microprocessor write timings. Register contents serve as input to an
internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the device is similar
to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV017 is programmed by executing the program command sequence. This will invoke the Embedded
Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is
accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which
is an internal algorithm that automatically preprograms the array if it is not already programmed before executing
the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell
margins.
Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV017 is erased when shipped from the factory.
The MBM29F017A device also features hardware sector group protection. This feature will disable both program
and erase operations in any combination of eight sectior groups of memory. A sector group consists of four
adjacect sectors grouped in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31.
Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of
time to read data from or program data to a mom-busy sector. Thus, true background erase can be achieved.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
comleted, the device internally resets to the read mode.
The MBM29LV017 also has a hardware RESET pin. When this pin is driven low, execution of any Embedded
Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the
read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during
the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read
mode and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up
firmware from the Flash memory.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29LV017 memory electrically erases all bits within
a sector simultaneously via Fowler-Nordhiem tunneling. The bytes are programmed one byte at a time using
the EPROM programming mechanism of hot electron injection.
3
PCB Design
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