† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
TA = 25°C
MIN
VCC
VIH
VIL
VI
VO
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
0
0
4.5
2
0.8
VCC
VCC
–24
24
10
0
0
MAX
5.5
–40°C TO
85°C
MIN
4.5
2
0.8
VCC
VCC
–24
24
10
0
0
MAX
5.5
–55°C TO
125°C
MIN
4.5
2
0.8
VCC
VCC
–24
24
10
MAX
5.5
V
V
V
V
V
mA
mA
ns/V
UNIT
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50
µA
IOH = –24 mA
IOH = –50 mA‡
IOH = –75 mA‡
IOL = 50
µA
VOL
VI = VIH or VIL
IOL = 24 mA
IOL = 50 mA‡
IOL = 75 mA‡
IO = 0
VCC
4.5 V
4.5 V
5.5 V
5.5 V
4.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
4.5 V to 5.5 V
±0.1
4
2.4
10
1.65
±1
40
2.8
10
±1
80
3
10
µA
µA
mA
pF
0.1
0.36
3.85
0.1
0.44
0.1
0.5
1.65
V
TA = 25°C
MIN
4.4
3.94
MAX
–40°C TO
85°C
MIN
4.4
3.8
MAX
–55°C TO
125°C
MIN
4.4
3.7
3.85
V
MAX
UNIT
VOH
VI = VIH or VIL
II
ICC
∆I
CC
Ci
VI = VCC or GND
VI = VCC or GND,
VI = VCC – 2.1 V
‡ Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
CD54ACT08, CD74ACT08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS312B – JANUARY 2001 – REVISED JUNE 2002
ACT INPUT LOAD TABLE
INPUT
A or B
UNIT LOAD
0.3
Unit load is
∆I
CC limit specified
in electrical characteristics
table (e.g., 2.4 mA at 25°C).
switching characteristics over recommended operating free-air
V
CC
= 5 V
±
0.5 V, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
temperature
–55°C TO
125°C
MIN
3.2
3.2
MAX
12.9
12.9
range,
–40°C TO
85°C
MIN
MAX
11.7
11.7
UNIT
A or B
Y
3.3
3.3
ns
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TYP
50
UNIT
pF
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
CD54ACT08, CD74ACT08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS312B – JANUARY 2001 – REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION
R1 = 500
Ω
S1
2
×
VCC
Open
GND
R2 = 500
Ω
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2
×
VCC
GND
From Output
Under Test
CL = 50 pF
(see Note A)
tw
3V
LOAD CIRCUIT
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
0V
tsu
Data
Input
1.5 V
10%
90%
tr
th
90%
3V
1.5 V
10% 0 V
tf
1.5 V
0V
CLR
Input
3V
1.5 V
0V
trec
3V
Reference
Input
CLK
1.5 V
0V
VOLTAGE WAVEFORMS
RECOVERY TIME
3V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
Input
1.5 V
tPLH
1.5 V
0V
tPHL
90%
tr
90%
VOH
50% VCC
10%
VOL
tf
90%
tr
VOH
VOL
Output
Control
tPZL
3V
1.5 V
1.5 V
0V
tPLZ
20% VCC
tPZH
≈V
CC
20% VCC
VOL
tPHZ
80% VCC
VOH
80% VCC
≈0
V
In-Phase
Output
50%
10%
tPHL
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPLH
50% VCC
10%
tf
50%
10%
Out-of-Phase
Output
90%
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
CD54ACT08F3A
CD74ACT08E
CD74ACT08EE4
CD74ACT08M
CD74ACT08M96
CD74ACT08M96E4
CD74ACT08M96G4
CD74ACT08ME4
CD74ACT08MG4
Status
(1)
Package Type Package Pins Package
Drawing
Qty
CDIP
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
J
N
N
D
D
D
D
D
D
14
14
14
14
14
14
14
14
14
1
25
25
50
2500
2500
2500
50
50
Eco Plan
(2)
Lead/Ball Finish
A42
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
MSL Peak Temp
(3)
Op Temp (°C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
Top-Side Markings
(4)
Samples
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TBD
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
CD54ACT08F3A
CD74ACT08E
CD74ACT08E
ACT08M
ACT08M
ACT08M
ACT08M
ACT08M
ACT08M
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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