Features
H
H
H
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H
H
H
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H
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H
H
18.1SPECint95, estimates 12.3 SPECfp95 @400Mhz (PC755B)
15.7SPECint95, 9SPECfp95 @350Mhz (PC745B)
733 MIPS @ 400Mhz (PC755B) et 641 MIPS@350Mhz (PC745B)
Selectable bus clock (12 CPU bus dividers up to 10x)
P
D
typical 6,4W @ 400Mhz, full operating conditions.
Nap, doze and sleep modes for power savings
Superscalar (3 instructions per clock cycle) (two instruction + branch)
4 PetaByte virtual memory, 4 Gigabytes of physical memory.
64-bit data and 32-bit address bus interface.
32KB instruction and data cache.
Six independent execution units.
Write-back and write-through operations.
f
int
max = 400Mhz (TBC)
f
bus
max = 100Mhz
Voltage I/O 1,8V/3,3V ; voltage int 2.0 V
PowerPC755B/745B
RISC MICROPRO-
CESSOR
Preliminary
Specification
α-site
Description
PC755B and PC745B PowerPC microprocessors are high-performance, low-power, 32-bit
implementations of the PowerPC Reduced Instruction Set Computer (RISC) architecture, spe-
cially enhanced for embedded applications.
PC755B and PC745B microprocessors differ only in that the PC755B features an enhanced,
dedicated L2 cache interface with on-chip L2 tags. The PC755B is a drop-in replacement fo r the
award winning PowerPC 750
TM
microprocessor and is footprint and user software code compat-
ible with the MPC7400 microprocessor withAltiVec
TM
technology. The PC745B is a drop-in
replacement for the PowerPC 740
TM
microprocessor and is also footprint and user soltware
code compatible with the PowerPC 603e
TM
microprocessor. PC755B/745B microprocessors
provide on-chip debug support and are fully JTAG-compliant.
The PC745B microprocessor is pin compatible with the TSPC603e family.
PC755B/745B
ZF suffix
ZF suffix
PBGA255
Flip-Chip Plastic Ball Grid Array
PBGA360
Flip-Chip Plastic Ball Grid Array
Screening
This product is manufactured in full compliance with :
H
CBGA upscreenings based upon ATMEL-Grenoble standards
H
Full military temperature range (Tj=-55
o
C,+125
o
C)
industrial temperature range (Tj=-40
o
C,+110
o
C)
September 2000
1/48
SUMMARY
A. GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . 3
1. SIMPLIFIED BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . 3
1.1. General parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. PIN ASSIGNEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2. Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . 25
4.2.1. Clock AC Specifications . . . . . . . . . . . . . . . . . . . . . 25
4.2.2. Processor Bus AC Specifications . . . . . . . . . . . . . 26
4.2.3. L2 Clock AC Specifications . . . . . . . . . . . . . . . . . . 28
4.2.4. L2 Bus Input AC Specifications . . . . . . . . . . . . . . 31
4.2.5. IEEE 1149.1 AC Timing Specifications . . . . . . . . 33
5. PREPARATION FOR DELIVERY . . . . . . . . . . . . . . . . . . 37
2.1. PINOUT LISTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1. Pinout listing for the PC745B, 255 PBGA . . . . . . . 9
2.1.2. Pinout listing for the PC755B, 360P PBGA
package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2. Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2. Certificate of compliance . . . . . . . . . . . . . . . . . . . . 37
6. HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7. PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . 38
B. DETAILED SPECIFICATION . . . . . . . . . . . . . . . . 16
1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2. APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . . . . . . 16
3. REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2. Design and construction . . . . . . . . . . . . . . . . . . . . 16
3.2.1. Terminal connections . . . . . . . . . . . . . . . . . . . . . . 16
3.2.2. Absolute maximum rating . . . . . . . . . . . . . . . . . . . 16
3.3. Recommendated operating conditions . . . . . . . 18
3.4. Thermal characteristics . . . . . . . . . . . . . . . . . . . . . 18
3.4.1. Package characteristics . . . . . . . . . . . . . . . . . . . . . 18
3.4.2. Thermal management assistance . . . . . . . . . . . . 19
3.4.3. Thermal Management Information . . . . . . . . . . . . 20
3.5. Power consideration . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5.1. Power management . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5.2. Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . 24
4.1. Static characteristics . . . . . . . . . . . . . . . . . . . . . . . 24
7.1. Parameters for the PC745B . . . . . . . . . . . . . . . . . . 38
7.1.1. Package Parameters for the PC745B PBGA . . . 38
7.1.2. Mechanical Dimensions of the PC745B PBGA
package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2. Parameters for the PC755B PBGA . . . . . . . . . . . . 40
7.2.1. Package parameter for the PC755B PBGA . . . . 40
7.2.2. Mechanical Dimensions of the PC755B PBGA . 40
8. CLOCK RELATIONSHIPS CHOICE . . . . . . . . . . . . . . . 41
9. SYSTEM DESIGN INFORMATION . . . . . . . . . . . . . . . . . 43
9.1. PLL Power Supply Filtering . . . . . . . . . . . . . . . . . . 43
9.2. Power Supply Voltage Sequencing . . . . . . . . . . . 43
9.3. Decoupling Recommendations . . . . . . . . . . . . . . 43
9.4. Connection Recommendations . . . . . . . . . . . . . . 44
9.5. Output Buffer DC Impedance . . . . . . . . . . . . . . . . 44
9.6. Pull-up Resistor Requirements . . . . . . . . . . . . . . 45
10. DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11. DIFFERENCES WITH COMMERCIAL PART . . . . . . . 46
12. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . 47
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PC755B/745B
PC755B/745B
A. GENERAL DESCRIPTION
1. SIMPLIFIED BLOCK DIAGRAM
The PC755B is targeted for low power systems and supports the following power management features-doze, nap, sleep, and
dynamic power management. The PC755B consists of a processor core and an internal L2 Tag combined with a dedicated L2 cache
interface and a 60x bus.
Control Unit
Instruction Fetch
Branch Unit
Completion
32K ICache
System Unit
Dispatch
BHT/BTIC
GPRs
FXU1
FXU2
Rename
Buffers
LSU
FPRs
Rename
Buffers
FPU
L2 Cache
32K DCache
L2 Tags
BIU
60x BIU
Not In The PC745B
Figure 1 : PC755B Block Diagram
3/48
1.1. General parameters
The following list provides a summary of the general parameters of the PC755B:
Technology
0.22 m CMOS, six-layer metal
Die size
Transistor count
Logic design
PC745B:
6.61 mm x 7.73 mm (51 mm
2
)
6.75 million
Fully-staticPackages
Surface mount 255 plastic ball grid array (PBGA)
PC755B:
Surface mount 360 plastic ball grid array (PBGA)
Core power supply: 2.0V 100 mV dc (nominal; see table 5 for recommended operating conditions)
I/O power supply
1.8V 100 mV dc or
2.0V 100 mV dc or
3.3V 165mV dc (input thresholds are configuration pin selectable)
1.2. Features
This section summarizes features of the PC755B’s implementation of the PowerPC architecture. Major features of the PC755B are as
follows:
D
Branch processing unit
- Four instructions fetched per clock
- One branch processed per cycle (plus resolving 2 speculations)
- Up to 1 speculative stream in execution, 1 additional speculative stream in fetch
- 512-entry branch history table (BHT) for dynamic prediction
- 64-entry, 4-way set associative Branch Target Instruction Cache (BTIC) for eliminating branch delay slots
D
Dispatch unit
- Full hardware detection of dependencies (resolved in the execution units)
- Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-
point)
- Serialization control (predispatch, postdispatch, execution serialization)
D
Decode
- Register file access
- Forwarding control
- Partial instruction decode
D
Completion
- 6 entry completion buffer
- Instruction tracking and peak completion of two instructions per cycle
- Completion of instructions in program order while supporting out-of- order instruction execution, completion serialization and
all instruction flow changes
D
Fixed Point Units (FXUs) that share 32 GPRs for integer operands
- Fixed Point Unit 1 (FXU1)-multiply, divide, shift, rotate, arithmetic, logical
- Fixed Point Unit 2 (FXU2)-shift, rotate, arithmetic, logical
- Single-cycle arithmetic, shifts, rotates, logical
- Multiply and divide support (multi-cycle)
- Early out multiply
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PC755B/745B
PC755B/745B
D
Floating-point unit and a 32-entry FPR file
- Support for IEEE-754 standard single and double precision floating point arithmetic
- Hardware support for divide
- Hardware support for denormalized numbers
- Single-entry reservation station
- Supports non-IEEE mode for time-critical operations
D
System unit
- Executes CR logical instructions and miscellaneous system instructions
- Special register transfer instructions
D
Load/store unit
- One cycle load or store cache access (byte, half-word, word, double-word)
- Effective address generation
- Hits under misses (one outstanding miss)
- Single-cycle unaligned access within double word boundary
- Alignment, zero padding, sign extend for integer register file
- Floating point internal format conversion (alignment, normalization)
- Sequencing for load/store multiples and string operations
- Store gathering
- Cache and TLB instructions
- Big and Little-endian byte addressing supported
- Misaligned Little-endian supported
D
Level 1 Cache structure
- 32K, 32-byte line, 8-way set associative instruction cache (iL1)
- 32K, 32-byte line, 8-way set associative data cache (dL1)
- Cache locking for both instruction and data caches, selectable by group of ways
- Single-cycle cache access
- Pseudo least-recently used (PLRU) replacement
- Copy-back or Write Through data cache (on a page per page basis)
- Supports all PowerPC memory coherency modes
- Non-Blocking instruction and data cache (one outstanding miss under hits)
- No snooping of instruction cache
D
Level 2 (L2) Cache Interface (not implemented on PC745B)
- Internal L2 cache controller and tags; external data SRAMs
- 256K, 512K, and 1Mbyte 2-way set associative L2 cache support
- Copyback or write-through data cache (on a page basis, or for all L2)
- Instruction-only mode and data-only mode.
- 64byte (256K/512K) or 128byte (1M) sectored line size
- Supports flow through (register-buffer) synchronous burst SRAMs, pipelined (register-register) synchronous burst SRAMs
(3-1-1-1 or strobeless 4-1-1-1) and pipelined (register-register) late-write synchronous burst SRAMs
- L2 configurable to direct mapped SRAM interface or split cache/direct mapped or private memory
- Core-to-L2 frequency divisors of 1, 1.5, 2, 2.5, and 3 supported
- 64 bit data bus
- Selectable interface voltages of 1.8V/2.0V and 3.3V
- Parity checking on both L2 address and data
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