Fact Sheet
MPC750FACT/D
REV. 6
M
OTOROLA
P
OWER
PC 750
™
AND
P
OWER
PC 740
™
M
ICROPROCESSORS
The PowerPC 750 and PowerPC 740 microprocessors are low-power 32-bit implementations of the
PowerPC Reduced Instruction Set Computer (RISC) architecture. The PowerPC 750 and the PowerPC 740
microprocessors differ only in that the PowerPC 750 features a dedicated L2 cache interface with on-chip L2
tags. Both are software-compatible and bus-compatible with the PowerPC 603e™ and MPC7400 micro-
processors, and the PowerPC 740 is pin-compatible as well. PowerPC 750/740 microprocessors are fully
JTAG-compliant.
Superscalar Microprocessor
The PowerPC 750/740 microprocessors are superscalar, capable
of issuing three instructions per clock cycle into six independent
execution units:
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Motorola PowerPC 750
Microprocessor
Two integer units
Load/store unit
Floating-point unit
System register unit
Branch processing unit
The ability to execute multiple instructions in parallel, to
pipeline instructions, and the use of simple instructions with
rapid execution times yields maximum efficiency and throughput
for PowerPC 750/740 systems.
Power Management
The PowerPC 750/740 microprocessors feature a low-
power 2.6-volt or 1.9-volt design with three power-
saving modes—doze, nap and sleep. These
user-programmable modes progressively reduce the
power drawn by the processor.
These low-power microprocessors offer dynamic
power management to selectively activate functional
units as they are needed by the executing instructions.
Both microprocessors also provide a thermal assist unit
and instruction cache throttling for software-
controllable thermal management.
PowerPC 750/740 Microprocessor
Block Diagram
System Register
Unit
Branch Processing
Unit
Instruction
Unit
Integer Integer
Unit
Unit
Load/Store
Unit
Floating Point
Unit
MMU
Data Cache
MMU
Inst. Cache
Cache and MMU Support
The PowerPC 750/740 microprocessors have separate
32-Kbyte, physically-addressed instruction and data
caches. Both caches are eight-way set-associative.
The additional dedicated L2 cache interface with on-
chip L2 tags (shown at right) is provided only by the
Bus Interface Unit
64b
Data
System Bus
32b
Address
64b
Data
L2 Cache
MPC750 Only
L2 Control / Tags
17b
Address
PowerPC 750 microprocessor. PowerPC 750/740 microprocessors contain separate memory management units
(MMUs) for instructions and data, supporting 4 Petabytes (2
52
) of virtual memory and 4 Gigabytes (2
32
) of physical
memory. Access privileges and memory protection are controlled on block or page granularities. Large, 128-entry
translation lookaside buffers (TLBs) provide efficient physical address translation and support for demand virtual-
memory management on both page- and variable-sized blocks.
Flexible Bus Interface
PowerPC 750/740 microprocessors have a 64-bit data bus and a 32-bit address bus. Support is included for burst, split
and pipelined transactions. The interface provides snooping for data cache coherency. Both microprocessors maintain
MEI coherency protocol in hardware, allowing access to system memory for additional caching bus masters, such as
DMA devices.
PowerPC 750/740 CPU Summary
PowerPC 740
200-266 MHz
PowerPC 740
300-333 MHz
PowerPC 750
200-266 MHz
PowerPC 750
300-400 MHz
CPU Speeds – Internal
CPU Bus Dividers
Bus Interface
Instructions per Clock
L1 Cache
L2 Cache
Core-to-L2 Frequency
Typical/Maximum
Power Dissipation
Die Size
Package
Process
Voltage
SPECint95 (estimated)
SPECfp95 (estimated)
Other Performance
Execution Units
200, 233 and 266 MHz
x3, x3.5, x4, x4.5, x5, x5.5,
x6, x6.5, x7 x7.5, x8
,
64 bits
3 (2 + Branch)
32-Kbyte instruction
32-Kbyte data
—
—
5.7W/7.9W @ 266 MHz
67 mm
2
255 CBGA
0.29µ 5LM CMOS
3.3V i/o, 2.6V internal
11.5 @ 266 MHz
6.9 @ 266 MHz
488 MIPS @ 266 MHz
300 and 333 MHz
x3, x3.5, x4, x4.5, x5, x5.5,
x6, x6.5, x7 x7.5, x8
,
64 bits
3 (2 + Branch)
32-Kbyte instruction
32-Kbyte data
—
—
4.2W/6.0W @ 333 MHz
67 mm
2
255 CBGA
0.25µ 5LM CMOS
3.3V i/o, 1.9V internal
14.4 @ 333 MHz
8.7 @ 333 MHz
610 MIPS @ 333 MHz
200, 233 and 266 MHz
x3, x3.5, x4, x4.5, x5, x5.5,
x6, x6.5, x7 x7.5, x8
,
64 bits
3 (2 + Branch)
32-Kbyte instruction
32-Kbyte data
256, 512 Kbyte
1 Mbyte
1:1, 1.5:1, 2:1, 2.5:1, 3:1
5.7W/7.9W @ 266 MHz
67 mm
2
255 CBGA
0.29µ 5LM CMOS
3.3V i/o, 2.6V internal
12.0 @ 266 MHz
7.4 @ 266 MHz
488 MIPS @ 266 MHz
300, 333, 366 and 400 MHz
x3, x3.5, x4, x4.5, x5, x5.5,
x6, x6.5, x7 x7.5, x8
,
64 bits
3 (2 + Branch)
32-Kbyte instruction
32-Kbyte data
256, 512 Kbyte
1 Mbyte
1:1, 1.5:1, 2:1, 2.5:1, 3:1
5.8W/8.0W @ 400 MHz
67 mm
2
255 CBGA
0.25µ 5LM CMOS
3.3V i/o, 1.9V internal
18.8 @ 400 MHz
12.2 @ 400 MHz
733 MIPS @ 400 MHz
Integer, Floating-Point, Branch, Integer, Floating-Point, Branch, Integer, Floating-Point, Branch, Integer, Floating-Point, Branch,
Load/Store, System Register
Load/Store, System Register
Load/Store, System Register
Load/Store, System Register
Contact Information
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Motorola offers user’s manuals,
application notes and sample
code for all of its processors.
In addition, local support for these
products is also provided.
This information can be found at:
PowerPC 1xx, 6xx and 7xx Part Number Key
MPC
750
100, 600, or 700
Series Device Number
(106, 107 603, 740, 745,
,
750, 755)
Product Code
PPC Sample
XPC XC qualified
MPC Qualified
A
RX
200
Frequency
2-3 digits
L
H
Revision
Package
FE CQFP
RX CBGA w/o lid
PX PBGA w/o lid
http://motorola.com/PowerPC/
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For all other inquiries about Motorola
products, please contact the Motorola
Customer Response Center at:
Part/Module Modifier
A Alpha (original)
B DGO process
E 603 Enhanced Performance
P Enhanced & Lower Voltage
R 603e in HiP3 process
Application Modifier
Bus Ratio
C 2:1 (106 only)
D 5:2 (106 only)
L Full spec all modes
-or-
Application Relief
R 105°
T ext. temp. (-40° to 105°)
Phone: 800-521-6274 or
http://motorola.com/semiconductors
©2000 Motorola, Inc. All rights reserved. Printed in the U.S.A. Motorola and the
are registered trademarks of Motorola, Inc. PowerPC, the PowerPC logo, PowerPC 603e, PowerPC 740 and PowerPC 750 are trademarks of International
Business Machines Corporation and used under license therefrom. This document contains information on a new product under development. Specifications and information herein are subject to change without notice.
1ATX35906-6 Printed in USA 5/00 Hibbert LITRISC
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