K4D551638F-TC
256M GDDR SDRAM
256Mbit GDDR SDRAM
Revision 2.1
April 2005
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
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Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev 2.1 (Apr. 2005)
K4D551638F-TC
Revision History
Revision 2.1(April 29, 2005)
• Mofidied CKE input functional description on page 5.
• Added K4D551638F-TC60 from the data sheet.
256M GDDR SDRAM
Revision 2.0(March 24, 2005)
• Removed K4D551638F-TC60 from the data sheet.
• Typo corrected.
Revision 1.9(February 24, 2005)
• Typo corrected.
Revision 1.8 (August 30, 2004)
• DC Spec defined for -TC33/36/40
Revision 1.7 (June 15, 2004)
• Changed VDD/VDDQ of K4D551638F-TC33 from 2.8V + 0.1V to 2.8V(min)/2.95V(max)
• Spec for -TC33/36/40 still in target
Revision 1.6 (March 31, 2004)
• AC Changes : Refer to the AC characteristics of page 13 and 14.
Revision 1.5 (March 18, 2004)
• Added K4D551638F-TC33 in the data sheet.
• Target spec defined for -TC33
Revision 1.4 (February 27, 2004)
• Added K4D551638F-TC36/40 in the data sheet.
• Target spec defined for -TC36/40
Revision 1.3 (December 5, 2003)
• Changed VDD/VDDQ of K4D551638F-TC50 from 2.5V + 5% to 2.6V + 0.1V
Revision 1.2 (November 11, 2003)
• "Wrtie-Interrupted by Read Function" is supported
Revision 1.1 (October 13, 2003)
• Defined ICC7 value
Revision 1.0 (October 10, 2003)
• Defined DC spec
• Changed part number of 16Mx16 GDDR F-die from K4D561638F-TC to K4D551638F-TC.
Revision 0.1 (October 2, 2003) -
Target Spec
• Added Lead free package part number in the data sheet.
• Removed K4D561638F-TC40 from the data sheet.
- 2 -
Rev 2.1 (Apr. 2005)
K4D551638F-TC
256M GDDR SDRAM
4M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
• 2.6V + 0.1V power supply for device operation
• 2.6V + 0.1V power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• Differential clock input
• No Write-Interrupted by Read Function
• 2 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 64ms refresh period (8K cycle)
• 66pin TSOP-II
• Maximum clock frequency up to 300MHz
• Maximum data rate up to 600Mbps/pin
ORDERING INFORMATION
Part NO.
K4D551638F-TC33
K4D551638F-TC36
K4D551638F-TC40
K4D551638F-TC50
K4D551638F-TC60*
Max Freq.
300MHz
275MHz
250MHz
200MHz
166MHz
Max Data Rate
600Mbps/pin
550Mbps/pin
500Mbps/pin
400Mbps/pin
333Mbps/pin
SSTL_2
Interface
VDD & VDDQ
2.8V ~ 2.95V
2.8V+0.1V
2.6V+0.1V
2.5V+0.125V
66pin TSOP-II
Package
1. K4D551638F-LC is the Lead Free package part number.
2. For the K4D551638F-TC60, VDD & VDDQ = 2.5V + 5%
3. For the K4D551638F-TC36, VDD & VDDQ = 2.8V + 0.1V
4. For the K4D551638F-TC33, VDD & VDDQ = 2.8V ~ 2.95V
GENERAL DESCRIPTION
FOR 4M x 16Bit x 4 Bank GDDR SDRAM
The K4D551638F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 4,194,304 words by
16 bits, fabricated with SAMSUNG
’
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 1.1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 3 -
Rev 2.1 (Apr. 2005)
K4D551638F-TC
PIN CONFIGURATION
(Top View)
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DDQ
LDQS
NC
V
DD
NC
LDM
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
256M GDDR SDRAM
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm Pin Pitch)
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
PIN DESCRIPTION
CK,CK
CKE
CS
RAS
CAS
WE
L(U)DQS
L(U)DM
RFU
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe
Data Mask
Reserved for Future Use
BA
0
, BA
1
A
0
~A
12
DQ
0
~ DQ
15
V
DD
V
SS
V
DDQ
V
SSQ
NC
VREF
Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ
’
s
Ground for DQ
’
s
No Connection
Reference voltage
- 4 -
Rev 2.1 (Apr. 2005)
K4D551638F-TC
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Sym-
CK, CK*1
Input
256M GDDR SDRAM
Type
Function
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s
that are sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal when low. By
deactivating the clock, CKE low indicates the Power down mode or Self refresh
mode.CKE is synchronous for Power down entry and exit, and for Self refresh
entry. CKE is asynchronous for Self refresh exit, and for output disable. CKE must
be maintained high through Read and Write accesses. Input buffers, excluding CK,
CK and CKE are disbled during Power down. Input buffers, excluding CKE are dis-
abled during Self refresh. CKE is an SSTL_2 input, but will detect a LVCMOS low
level after Vdd is applied upon 1st power up. After Vref has become stable during
the power on and intialization sequence, it must be maintained for proper opera-
tion of the CKE receiver. For proper Self refresh entry and exit, Vref must be main-
tained to this input.
CS enables the command decoder when low and disabled the command decoder
when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
Latches row addresses on the positive going edge of the CK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to
the data on DQ8-DQ15.
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM
correspons to the data on DQ8-DQ15.
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA12, Column addresses : CA0 ~ CA8.
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
Reference voltage for inputs, used for SSTL interface.
This pin is recommended to be left "No connection" on the device
CKE
Input
CS
Input
RAS
CAS
WE
Input
Input
Input
LDQS,UDQS
Input/Output
LDM,UDM
DQ0 ~ DQ15
BA0, BA1
A0 ~ A12
VDD/VSS
VDDQ/VSSQ
VREF
NC/RFU
Input
Input/Output
Input
Input
Power Supply
Power Supply
Power Supply
No connection/
Reserved for future use
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V
REF
to CK pin.
- 5 -
Rev 2.1 (Apr. 2005)
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