HM62W8127H Series
HM62W9127H Series
131072-word
×
8/9-bit High Speed CMOS Static RAM
Description
The HM62W8127H/HM62W9127H is an asynchronous 3.3 V operation high speed static RAM organized as
131,072-word
×
8/9-bit. It realize high speed access time (30/35/45 ns) with employing 0.8
µm
CMOS
process and high speed circuit designing technology. It is most appropriate for the application which requires
high speed, high density memory and wide bit width configuration, such as cache and buffer memory in
system. The HM62W8127H/HM62W9127H is packaged in 400-mil 32/36-pin SOJ for high density surface
mounting.
Features
•
Single 3.3 V supply: 3.3 V
±
0.3 V
•
Access time 30/35/45 ns (max)
•
Completely static memory
No clock or timing strobe required
•
Equal access and cycle times
•
Directly CMOS compatible
All inputs and outputs
•
400-mil 32/36-pin SOJ package
•
Center V
CC
and V
SS
type pinout
HM62W8127H/HM62W9127H Series
Ordering Information
Type No.
HM62W8127HJP-30
HM62W8127HJP-35
HM62W8127HJP-45
HM62W8127HLJP-30
HM62W8127HLJP-35
HM62W8127HLJP-45
HM62W9127HJP-30
HM62W9127HJP-35
HM62W9127HJP-45
HM62W9127HLJP-30
HM62W9127HLJP-35
HM62W9127HLJP-45
Access Time
30 ns
35 ns
45 ns
30 ns
35 ns
45 ns
30 ns
35 ns
45 ns
30 ns
35 ns
45 ns
400-mil 36-pin plastic SOJ (CP-36D)
Package
400-mil 32-pin plastic SOJ (CP-32DB)
2
HM62W8127H/HM62W9127H Series
Pin Arrangement
HM62W8127H Series
A3
A2
A1
A0
CS
I/O1
I/O2
V
CC
V
SS
I/O3
I/O4
WE
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top View)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A4
A5
A6
A7
OE
I/O8
I/O7
V
SS
V
CC
I/O6
I/O5
A8
A9
A10
A11
A12
NC
A3
A2
A1
A0
CS
I/O1
I/O2
V
CC
V
SS
I/O3
I/O4
WE
A16
A15
A14
A13
NC
HM62W9127H Series
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
(Top View)
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A4
A5
A6
A7
OE
I/O9
I/O8
I/O7
V
SS
V
CC
I/O6
I/O5
A8
A9
A10
A11
A12
NC
Pin Description
Pin Name
HM62W8127H
A0 – A16
I/O1 – I/O8
CS
WE
OE
V
CC
V
SS
—
HM62W9127H
A0 – A16
I/O1 – I/O9
CS
WE
OE
V
CC
V
SS
NC
Function
Address
Data input/output
Chip select
Write enable
Output enable
Power supply
Ground
No connection
3
HM62W8127H/HM62W9127H Series
Block Diagram
A4
A3
A2
A1
A0
A7
A6
A5
V
CC
Row
Decoder
Memory Matrix
256 rows x
512 x 8/9 columns
V
SS
CS
I/O1
.
.
.
I/O8/9
Column I/O
Input
Data
Control
Column Decoder
CS
A13 A12 A11 A16 A15 A14 A10 A9 A8
WE
CS
OE
CS
Absolute Maximum Ratings
Parameter
Supply voltage relative to V
SS
Voltage on any pin relative to V
SS
Power dissipation
Operating temperature
Storage temperature
Storage temperature under bias
Note:
Symbol
V
CC
V
T
P
T
Topr
Tstg
Tbias
Value
–0.5 to +4.6
–0.5
*1
to V
CC
+ 0.5
1.0
0 to +70
–55 to +125
–10 to +85
Unit
V
V
W
°C
°C
°C
1. –2.5 V for pulse width (under shoot)
≤
10 ns
4
HM62W8127H/HM62W9127H Series
Function Table
CS
H
L
L
L
OE
X
H
L
X
WE
X
H
H
L
V
CC
Current
I
SB
, I
SB1
I
CC
I
CC
I
CC
I/O
High-Z
High-Z
Output
Input
Ref. Cycle
Read cycle
Write cycle
Note: X: H or L
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Supply voltage
*2
Symbol
V
CC
V
SS
Input voltage
V
IH
V
IL
Min
3.0
0
2.0
–0.3
*1
Typ
3.3
0
—
—
Max
3.6
0
V
CC
+ 0.3
0.8
Unit
V
V
V
V
Notes: 1. –2.0 V for pulse width (under shoot)
≤
10 ns
2. The supply voltage with all V
CC
pins must be on the same level.
The supply voltage with all V
SS
pins must be on the same level.
5
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