P
RELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
1
Z89340
D
IGITAL
W
AVETABLE
E
NGINE
FEATURES
Part Number
Z89340
s
s
1
Speed
50 MHz
Package
160-Pin QFP
Supports 16- and 8-Bit Linear PCM Sampling, ADPCM,
and Wavetable Synthesis, Variable Playback Rates for
ADPCM
Internal 24-Bit Audio Accumulators
Addresses 16M x 16 Sample ROM Directly (No Paging
Necessary)
Jumperless Configurable ISA Bus Interface
Sound Blaster and OPL3 Register Compatibility,
MPU401 UART Mode Compatible
Built-In 64-Channel Bus-Mastering DMA Controller
FM Emulation
64 High-Speed Audio Processing Units (APUs) or 128
Half-Speed APUs
3-D Sound Capability
Downloadable Sample Capability
8-Channel, 20-Bit Linear PCM Audio Generator
Output Sampling Rates up to 50 kHz
Supports 16-, 18-, and 20-Bit Serial DACS – Greater
than 96 Db Dynamic Range
s
s
s
s
s
s
s
s
s
s
s
GENERAL DESCRIPTION
The Z89340 is a high-performance, programmable wave-
table engine designed for musical instruments, general
MIDI (Musical Instrument Digital Interface) sound modules,
digital mixing consoles with high-quality PC sound cards,
and computer-controlled multimedia applications.
This device features a 24-bit address bus for
addressing16-bit sample-storage ROM and DRAM (DRAM
refresh controller on-board), a 12x16 two’s-complement
scaler, eight 24-bit accumulators with clipping circuitry, a
2x8x16 interpolator to allow a high resolution of phase an-
gles between input samples, CD-quality sampling rates,
and 64 high-speed audio processing units (APUs) that can
be split into two low-speed APUs that operate at half the
sampling rate, allowing up to 128 notes to play simulta-
neously. All APUs are independent and can address any
part of data storage at any time.
The Z89340 can operate at output sampling rates up to 50
kHz, and offers eight channels of 16- to 20-bit serial output
data. The microprocessor interface allows full control of
frequency, amplitude, and sample data input to each oscil-
lator. The Z89340 features eight output registers, and their
contents can be sent to DAC or CODEC. Four of these can
be used for quadraphonic output, and have a panning
mechanism called Polar Pan that supports motion in all
four quadrants.
The other four output registers are used internally as ef-
fects channels, but can still send their data streams to a
DAC, a second Z89340, or other digital signal processor.
The Z89340 also has eight serial input data registers. In
addition, there are 24 stereo submix register pairs for use
in sending output data from one APU to be used as the in-
put to another.
In particular, the Z89340 is well-suited for 8- and 16-bit lin-
ear PCM recording/playback, wave synthesis, Sound
Blaster command set, and ADPCM (IMA/DVI) real-time de-
compression.
DS96DSP0201
PRELIMINARY
1-1
Z89340
Digital Wavetable Engine
PIN IDENTIFICATION
(Continued)
Table 1. 160-Pin QFP Pin Identification
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32–39
40
41
42
43
44–50
51
52
53
54
55
56
57
58
59
Symbol
GND
ROMADD11
ROMADD04
ROMADD12
ROMADD03
ROMADD13
ROMADD02
ROMADD14
ROMADD01
ROMADD15
ROMADD00
ROMADD16
WAVE_DATA_OE
WAVE_DATA_WRITE
WAVE_DATA_15
WAVE_DATA_00
WAVE_DATA_07
WAVE_DATA_08
WAVE_DATA_14
WAVE_DATA_01
WAVE_DATA_06
WAVE_DATA_09
WAVE_DATA_13
WAVE_DATA_02
WAVE_DATA_05
WAVE_DATA_10
WAVE_DATA_12
WAVE_DATA_03
WAVE_DATA_04
WAVE_DATA_11
ISA_MASTER16
ISA_SD_15–8
V
CC
GND
ISA_MEMW
ISA_MEMR
ISA_LA 17–23
ISA_BHE
ISA_DRQ_07
ISA_DACK_07
ISA_DRQ_06
ISA_DACK_06
ISA_DRQ_05
ISA_DACK_05
ISA_DRQ_00
ISA_DACK_00
Function
Ground
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
External Memory Output Enable
External Memory Write
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
ISA Master 16-Bit Transfer
ISA Data Bus
Power Supply
GND
ISA Memory Write
ISA Memory Read
ISA Address Bus
ISA Bus High Byte Enable
ISA DMA Request 07
ISA DMA Acknowledge 07
ISA DMA Request 06
ISA DMA Acknowledge 06
ISA DMA Request 05
ISA DMA Acknowledge 05
ISA DMA Request 00
ISA DMA Acknowledge 00
Direction
–
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Tri-State Input
Input/Output
–
–
Input/Output
Input/Output
Tri-State Output
Input/Output
Tri-State Output
Input
Tri-State Output
Input
Tri-State Output
Input
Tri-State Outputt
Input
1-4
PRELIMINARY
DS96DSP0201
stm32/stm8
京公网安备 11010802033920号
EEWORLD
