P R E L I M I N A R Y
Z89331
CP95TEL1400
P
RELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
Z89331
OTPDIGITAL
TELEVISIONCONTROLLER
FEATURES
n
Part
Number
Z89331
*General-Purpose
ROM
(KB)
24
RAM*
(Bytes)
640
Speed
(MHz)
12
n
n
n
Serial Interfacing I
2
C Port
Fully Customized Character Set
Character-Control and Closed-Caption Modes
Keypad User Control
TV Tuner Serial Interface
Direct Video Signals
Low-EMI Option
n
n
n
n
42-Pin SDIP Package
n
4.75- to 5.25-Volt Operating Range
n
0°C to +70°C Temperature Range
n
One-Time Programmable
n
GENERAL DESCRIPTION
The Z89331 One-Time Programmable (OTP) Digital
Television Controller is designed to provide complete
audio and video control of television receivers, video
recorders, and advanced on-screen display facilities. The
Z89331 features a Z89C00 RISC processor core that
controls on-board peripheral functions and registers using
the standard processor instruction set.
Character attributes can be controlled through two modes:
the on-screen display Character-Control Mode and the
Closed-Caption Mode. The Character-Control Mode
provides access to the full set of attribute controls, allowing
the modification of attributes on a character-by-character
basis. The insertion of control characters permits direction
of other character attributes. Closed-caption text can be
decoded directly from the composite video signal and
displayed on-screen with the assistance of the processor's
digital signal processing (DSP) capabilities.
The fully customized 512 character set, formatted in two
256 character banks, can be displayed with a host of
display attributes that include underlining, italics, blinking,
eight foreground/background colors, character position
offset delay, and background transparency.
Serial interfacing with the television tuner is provided
through the tuner serial port. Other serial devices, such as
digital channel tunning adjustments, may be accessed
through the industry-standard I
2
C port.
User control can be monitored through the keypad
port, or the 16-bit remote control capture register.
functions such as color and volume can be
controlled by eight 8-bit pulse width modulated
scanning
Receiver
directly
ports.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Power
Ground
Circuit
V
CC
GND
Device
V
DD
V
SS
CP95TEL1400 11/95
1
P R E L I M I N A R Y
Z89331
CP95TEL1400
PIN DESCRIPTIONS
Z89331
Pin
Name
V
CC
GND
IRIN
ADC[5:0]
a
PWM9
Z89331
42-Pin SDIP
34
13,30
36
–,9,10,11,12,2,8
1,2
Configuration
Direction
Reset
PWR
PWR
I
AI
OD
PWR
PWR
I
I
O
Function
+5 V
0V
Infrared Remote Capture Input
4-Bit Analog to Digital Converter
Input
b
14-Bit Pulse Width Modulator
Output
8-Bit Pulse Width Modulator
Output
Bit Programmable
Input/Output Ports
Bit Programmable
Input/Output Ports
I
2
C Clock I/O
I
2
C Data I/O
I
2
C Clock I/O
I
2
C Data I/O
Crystal Oscillator Input
Crystal Oscillator Output
Loop Filter
H_Sync
V_Sync
Device Reset
OSD Video Output
(Typically Drive B, G, and R Outputs)
OSD Blank Output
OSD Half Blank Output
R[1:0],G[1:0], and B[1:0]
Outputs of the RGB Matrix
Internal Processor SCLK
PWM[8:1]
c
Port0[F:0]
d
Port1[9:0]
e
–,–,–,3,4
5,6,7
21,–,–,–,–,–,
38,37,35,–,–,
15,8,40,39,11
–,16,12,20,
19,18,17,42,
41,14
41
42
39
40
31
32
29
26
27
33
22,23,24
25
21
37,14,17,
16,19,18
20
OD
B
OD
I
B
I
MSSCL
f
MSSCD
g
SSCL
h
SSCD
i
XTAL1
XTAL2
LPF
HSYNC
VSYNC
/RESET
V[3:1]
Blank
Half Blank
h
RGB Digital
Outputs
i
SCLK
k
BOD
BOD
BOD
BOD
AI
AO
AB
B
B
I
O
O
O
O
O
I
I
I
AI
AO
AB
I
I
I
O
O
I
I
I
Notes:
a) ADC1 input is shared with Port 17, ADC2 input Pin is shared with
Port 00. ADC3 input pin is shared with Port 05 and ADC4 input pin
is shared with Port 04.
b) ADC0 and ADC5 have a clamp circuit that facilitates Composite
video input.
c) PWM[8,7] is not available on the 42-pin DIP version.
d) Port0[F:A] is not available on the 42-pin DIP version.
e)
f)
g)
h)
i)
k)
Port19 is not available on the 42-pin DIP version.
SCL I/O pin is shared with Port01 or Port11.
SCD I/O pin is shared with Port02 or Port12.
Half Blank output is a function shared with Port0F.
Digital RGB outputs and the internal SCLK are shared with Port1[5:0].
Internal processor SCLK is shared with Port16.
4
FPGA/CPLD
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