IS25C32-2/3
IS25C64-2/3
32,768/65,536-BIT SPI SERIAL
ELECTRICALLY ERASABLE PROM
DESCRIPTION
FEATURES
• 2.1 MHz Clock Rate
• Low power CMOS
— Active current less than 3.0 mA (5.5V)
— Standby current less than 10 µA (5.5V)
• Low-voltage Operation
— IS25C64-3 & IS25C32-3 (Vcc = 2.5V to 5.5V)
— IS25C64-2 & IS25C32-2 (Vcc = 1.8V to 5.5V)
• Block Write Protection
— Protect 1/4, 1/2, or Entire Array
• 32 byte page write mode
• Serial Peripheral Interface (SPI) Compatible
— Supports SPI Modes 0 (0,0) and 3 (1,1)
• Self timed write cycles (5 ms Typical)
• High-reliability
— Endurance: 1 million cycles per byte
— Data retention: 100 years
— ESD protection >4000V
• Industrial temperature available
• 8-pin PDIP or SOIC, and 14-pin TSSOP Packages
ISSI
®
PRELIMINARY INFORMATION
NOVEMBER 2001
The IS25C64-2 is a 1.8V (1.8V-5.5V) 64K-bit (8192x8)
electrically Erasable PROM, IS25C64-3 is a 2.5V (2.5V-
5.5V) 64K bit (8192x8) Electrically Erasable PROM,
IS25C32-2 is a 1.8V (1.8V-5.5V) 32K-bit (4096x8) Electri-
cally Erasable PROM, IS25C32-3 is a 2.5V (2.5V-5.5V)
32K-bit (4096x8) Electrically Erasable PROM.
The IS25Cxx (IS25C64-2, IS25C64-3, IS25C32-2 and
IS25C32-3) family is a low-cost and low voltage/low power
SPI Serial EEPROM. It is fabricated using ISSI's ad-
vanced CMOS EEPROM technology and provides a low
power and low voltage operation for low power industrial
and commercial application. The IS25Cxx family is
available in 8 pin PDIP, 8 Pin SOIC, and 14 pin TSSOP
packages.
The IS25Cxx is enabled through the Chip Select pin (CS)
and accessed via a 3-wire interface consisting of Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK). All programming cycles are completely self-timed,
and no separate ERASE cycle is required before WRITE.
BLOCK WRITE protection is enabled by programming the
status register with one of four configurations of write
protection. Separate program enable and program disable
instructions are provided for additional data protection.
Hardware data protection is provided via the
WP
pin to
protect against inadvertent write attempts to the status
register. The
HOLD
pin can suspend communications
without re-initializing the serial sequence.
PRODUCT OFFERING OVERVIEW
Part No
IS25C64-2
IS25C64-3
IS25C32-2
IS25C32-3
Voltage
1.8V-5.5V
2.5V-5.5V
1.8V-5.5V
2.5V-5.5V
Speed
500 KHz
2.1MHz
500 KHz
2.1MHz
Standby ICC
< 5 µA
< 10 µA
< 5 µA
< 10 µA
Read ICC
1 mA
1 mA
1 mA
1 mA
Write ICC
3 mA
3 mA
3 mA
3 mA
Temperature
C,I
C,I
C,I
C,I
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
11/01/01
Rev. 00C
1
IS25C32-2/3
IS25C64-2/3
ISSI
14-pin TSSOP
®
PIN CONFIGURATION
8-Pin DIP and SOIC
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
NC
NC
NC
WP
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
HOLD
NC
NC
NC
SCK
SI
PIN DESCRIPTIONS
PIN DESCRIPTIONS
CS
SCK
SO
SI
GND
V
CC
WP
HOLD
NC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power
Write Protect
Suspends Serial Input
No Connect
Serial Clock (SCK)
- This pin is used to synchronize the
communication between the microcontroller and the
IS25C64, IS25C32. Op-codes, byte addresses, or data
present on the SI pin and latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge of
the SCK for SPI modes (0,0 & 1,1).
Serial Data Input (SI)
- The SI pin is used to input all op-
codes, byte addresses, and data to be written to the
device. Input data is latched on the rising edge of the
serial clock for SPI modes (0,0 & 1,1).
Serial Data Output (SO)
- The SO pin is used to transfer
data out of the device. During a read cycle, data is shifted
out on the falling edge of the serial clock for SPI modes (0,0
& 1,1).
Chip Select (CS):
When the
CS
pin is low, the device is
enabled. When the
CS
pin is high the device is disabled.
CS
high takes the SO output pin to high impedance and
forces the devices into a Standby Mode (unless an
internal write operation is underway). The devices draws
zero current in the Standby mode. A high-to-low transition
on
CS
is required prior to any sequence being initiated. A
low-to-high transition on
CS
after a valid write sequence is
what initiates an internal write cycle.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/01/01
IS25C32-2/3
IS25C64-2/3
PIN DESCRIPTIONS Continued:
Write Protect (WP)
- The
WP
Pin will allow normal read/
write operations when held high. When
WP
is tied low and
the WPEN bit in the status register is set to "1", all write
operations to the status register are inhibited.
WP
going
low while CS is still low will interrupt a write to the status
register. If the internal write cycle has already been
initiated,
WP
going low will have no effect on any write
operation to the status register. The
WP
pin function is
blocked when the WPEN bit is set to 0. Figure 10
illustrates the
WP
timing sequence during a write opera-
tion.
Hold (HOLD):
The
HOLD
pin is used to pause transmis-
sion to the device while in the middle of a serial sequence
without having to retransmit entire sequence at a later
time. To pause,
HOLD
must be brought low while SCK is
low. The SO pin is in a high impedance state during the
time the part is paused, and transition on the SI pins will
be ignored. To resume communication,
HOLD
is brought
high, while SCK is low. (HOLD should be held high any
time this function is not being used.)
HOLD
may be tied
high directly to Vcc or tied to Vcc through a resistor. The
HOLD
Timing Diagram illustrates hold timing sequence.
ISSI
SERIAL INTERFACE DESCRIPTION
MASTER:
This device that generates the serial clock.
®
SLAVE:
Because the Serial Clock pin (SCK) is always an
input, the device always operates as a slave.
MSB:
The Most Significant Bit (MSB) is the first bit
transmitted and received.
SERIAL OP-CODE:
After the device is selected with CS
going low, the first byte will be received. This byte contains
the op-code that defines the operations to be performed.
INVALID OP-CODE:
If an invalid op-code is received, no
data will be shifted into the device, and the serial output pin
(SO) will remain in a high impedance state until the falling
edge of CS is detected again. This will reinitialize the serial
communications.
BLOCK DIAGRAM
VCC
GND
STATUS
REGISTER
8192 x 8/4096 x 8
MEMORY ARRAY
DATA
REGISTER
SI
MODE
DECODE
LOGIC
ADDRESS
DECODER
OUTPUT
BUFFER
CS
WP
SCK
CLOCK
so
HOLD
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
11/01/01
Rev. 00C
3
IS25C32-2/3
IS25C64-2/3
FUNCTIONAL DESCRIPTIONS
The IS25C32/64 utilizes an 8-bit instruction register. The
list of instructions and their operation codes are contained
in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to low
CS transition.
ISSI
Bit
Bit 0 (RDY)
®
Table 3. Read Status Register Bit Definition
Definition
Bit 0 = 0 (RDY) indicates the device is
READY. Bit 0 = 1 indicates the write
cycle is in progress.
Bit 1 = 0 indicates the device is not
WRITE ENABLED. Bit 1 = 1 indicates
the device is WRITE ENABLED.
See Table 4
See Table 4
Bit 1(WEN)
Table 1. Instruction Set
Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Instruction
Format
Bit 2 (BPO)
Operation
Bit 3 (BP1)
0000 X110
Set Write Enable Latch
0000 X100
Reset Write Enable Latch
0000 X101
Read Status Register
0000 X001
Write Status Register
0000 X011 Read Data from Memory Array
0000 X010
Write Data to Memory Array
Bits 4 - 6 are 0s when the device is not an internal write cycle.
Bits 7 (WPEN) See Table 5.
Bits 0-7 are 1s during an internal write cycle.
WRITE ENABLE (WREN):
This device will power-up in
the write disable state when VCC is applied. All program-
ming instructions must therefore be preceded by a Write
Enable instruction.
WRITE DISABLE (WRDI):
To protect the device against
inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is indepen-
dent of the status of the
WP
pin.
READ STATUS REGISTER (RDSR):
The Read Status Register instruction provides access to
the status register. The READY/BUSY and Write Enable
status of the device can be determined by the RDSR
instruction. Similarly, the Block Write Protection bits
indicate the extent of protection employed. These bits are
set by using the WRSR instruction.
WRITE STATUS REGISTER (WRSR):
The WRSR in-
struction allows the user to select one of four levels of
protection. The device is divided into four array seg-
ments. One quarter (1/4), one half (1/2) or all of the
memory segments can be protected. Any of the data
within any selected segment will therefore be READ only.
The block write protection levels and corresponding
status register control bits are shown in Table 4.
The three bits, BP, BP1 and WPEN are nonvolatile
cells that have the same properties and functions as
the regular memory cells (e.g. WREN, twc, RDSR).
Table 4. Status Register Format
Status
Register
Bits
Level
BP1
0
0
1
1
BP0
0
1
0
1
0
1(1/4)
2(1/2)
3(All)
Array Addresses Protected
IS25C32
None
0C00
-0FFF
0800
-0FFF
0000
-0FFF
IS25C64
None
1800
-1FFF
1000
-1FFF
0000
-1FFF
Table 2. Status Register Format
Bit 7
WPEN
Bit 6 Bit 5 Bit 4
x
x
x
Bit 3 Bit 2 Bit1 Bit 0
BP1 BP0 WEN
RDY
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/01/01
IS25C32-2/3
IS25C64-2/3
The WRSR instruction also allows the user to enable or
disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protec-
tion is enabled when the
WP
pin is low and the WPEN bit
is '"1". Hardware write protection is disabled when either
the
WP
pin is high or the WPEN bit is "0". When the device
is hardware write protected, writes to the Status Register,
including the Block Protect bits and the WPEN bit, and the
block-protected sections in the memory array are dis-
abled. Writes are only allowed to sections of the memory
which are not block-protected.
Note: When the WPEN bit is hardware write protected,
it cannot be changed back to "0", as long as the
WP
pin
is held low.
ISSI
®
WRITE SEQUENCE (READ):
In order to program the
device, two sperate instructions must be executed.
First, the device must be write enabled via the Write
Enable (WREN) Instruction. Then a Write (WRITE)
Instruction may be executed. Also the address of the
memory location(s) to be programmed must be outside
the protected address field location selected by the
Block Write Protection Level. During an internal write
cycle, all commands will be ignored except the RDSR
instruction.
A Write Instruction requires the following sequence.
After the
CS
line is pulled low to select the device, the
WRITE op-code is transmitted via the SI line followed
by the byte address (A15-A0) and the data (D7-D0) to
be programmed (Refer to Table 6). Programming will
start after the
CS
pin is brought high. (The Low to High
transition of the
CS
pin must occur during the SCK low-
time immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be deter-
mined by initiating a READ STATUS REGISTER
(RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still
in progress. If Bit 0 = 0 , the WRITE cycle has ended.
Only the READ STATUS REGISTER instruction is
enabled during the WRITE programming cycle.
The device is capable of the 32-byte PAGE WRITE
operation. After each byte of data is received, the five
low order address bits are internally incremented by
one; the high order bits of the address will remain
constant. If more than 32 bytes of data are transmit-
ted, the address counter will roll over the previously
written data will be overwritten. The device is auto-
matically returned to the write disable state at the
completion of a WRITE cycle.
NOTE:
If the device is not Write enabled (WREN), the
device will ignore the Write instruction and will return to
the standby state, when
CS
is brought high. A new
CS
falling edge is required to re-initiate the serial communi-
cation.
Table 5. WPEN Operation
WPEN
WP
WEN
Protected
Blocks
Unprotected Protected
Blocks
Register
0
0
1
1
X
X
X
X
Low
Low
High
High
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Protected
Protected
Writable
READ SEQUENCE (READ):
Reading the device via
the SO (Serial Output) pin requires the following
sequence. After the
CS
line is pulled low to select a
device, the READ op-code is transmitted via the SI line
followed by the byte address to be read (A15-A0, Refer
to Table 6). Upon completion, any data on the SI line
will be ignored. The data (D7-D0) at the specified
address is then shifted out onto the SO line. If only
one byte is to be read, the
CS
line should be driven
high after the data comes out. The READ sequence
can be continued since the byte address is automati-
cally incremented and data will continue to be shifted
out. When the highest address is reached, the address
counter will roll over to the lowest address allowing the
entire memory to be read in one continuous READ
cycle.
Table 6. Address Key
Name
A
N
Don't
Care Bits
IS25C32
A
11-
A
0
A
15-
A
12
IS25C64
A
12-
A
0
A
15-
A
13
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
11/01/01
Rev. 00C
5
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