PRELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
Z89302/04/06
D
IGITAL
T
ELEVISION
C
ONTROLLER
FEATURES
Device
Z89302
Z89304
Z89306
ROM
(KB)
24
16
12
RAM*
(Bytes)
640
640
640
Speed
MHz
12
12
12
s
s
s
s
s
s
s
1
0
°
C to +70
°
C Temperature Range
Fully Customized Character Set
Character-Control and Closed-Caption Modes
Keypad User Control
TV Tuner Serial Interface
Direct Video Signals
Note:
* General-Purpose
40-Pin DIP Packages
4.75- to 5.25-Volt Operating Range
s
GENERAL DESCRIPTION
The Z89302/04/06 Digital Television Controllers are
designed to provide complete audio and video control of
television receivers, video recorders, and advanced on-
screen display facilities. The Television Controllers feature
a Z89C00 RISC processor core that controls the on-board
peripheral functions and registers using the standard
processor instruction set.
Character attributes can be controlled through two modes:
the on-screen display Character-Control Mode and the
Closed-Caption Mode. The Character-Control Mode
provides access to the full set of attribute controls, allowing
the modification of attributes on a character-by-character
basis. The insertion of control characters permits direction
of other character attributes.
The fully customized 512 character set, formatted in two
256 character banks, can be displayed with a host of
display attributes that include underlining, italics, blinking,
eight foreground/background colors, character position
offset delay, and background transparency.
Serial interfacing with the television tuner is provided
through the tuner serial port. Other serial devices, such as
digital channel tuning adjustments, may be accessed
through the industry-standard I
2
C port.
User control can be monitored through the keypad
scanning port, or the 16-bit remote control capture
register. Receiver functions such as color and volume can
be directly controlled by eight 8-bit pulse width modulated
ports.
The Z89302/04/06 has two internal 12 MHz VCOs that are
referenced to a 32 kHz internal oscillator to provide the
system clock. In Sleep Mode, the controller uses the
32 kHz clock for the system clock to reduce power
consumption. The processor can be suspended by placing
it into STOP Mode when main power is not available for
low-power consumption.
CP96TEL1803 (9/96)
1
Z89302/04/06
Digital Television Controller
PRELIMINARY
PIN DESCRIPTIONS
Z89302/03/06/07
Reset
Configuration
PWR–
PWR–
I
I
O
O
I
I
Pin Name
V
CC
GND
IRIN
ADC[5:0]
PWM9
PWM[8:1]
Port0[F:0]
Port1[9:0]
SCL
b
SCD
c
XTAL1
XTAL2
LPF
HSYNC
VSYNC
/RESET
V[3:1]
Blank
Half Blank
d
RGB Digital
Outputs
e
SCLK
f
Function
+5V
0V
Infrared Remote Capture Input
4-Bit Analog to Digital
Converter Input
14-Bit Pulse Width Modulator
Output
8-Bit Pulse Width Modulator
Output
Bit Programmable Input/Output
Ports
Bit Programmable Input/Output
Ports
I
2
C Clock I/O
I
2
C Data I/O
Crystal Oscillator Input
Crystam Oscillator Output
Loop Filter
H_Sync
V_Sync
Device Reset
OSD Video Output (Typically
Drive B, G, and R Outputs)
OSD Blank Output
OSD Half Blank Output
R[1:0],G[1:0], and B[1:0]
Outputs of the RGB Matrix
Internal Processor SCLK
40-Pin, Z89302/04/06
29,–
31,–
2
–,9,8,4,27,34
1
–,–,40,39,38
–,–,–,–,–,–,13,12,11,10,9,8,7,6,5,4
–,3,27,20,19,18,17,16,15,14
5 or 15
6 or 16
30
32
33
21
22
28
23,24,25
26
–
19,18,17,14,12,3
Direction
I
nAI
OD/O
a
OD/O
a
B
B
BOD
BOD
AI
AO
AB
B
B
I
O
O
O
O
O
I
O
O
I
I
I
O
O
I
Notes:
a) Port19 is not available on the 40-pin DIP Version, Revision D is Push-Pull.
b) SCL I/O pin is shared with Port01 or Port11
c) SCD I/O pin is shared with Port02 or Port12
d) Half Blank output is a function shared with Port0F. Half Blank output is not available on the 40-pin DIP version.
e) Digital RGB outputs and the internal SCLK are shared with Port1[5:0].
f) Internal processor SCLK is shared with Port16.
4
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