K7N803601B
K7N803201B
K7N801801B
Document Title
256Kx36/x32 & 512Kx18 Pipelined NtRAM
TM
256Kx36 & 256Kx32 & 512Kx18-Bit Pipelined NtRAM
TM
Revision History
Rev. No.
0.0
0.1
0.2
1.0
History
1. Initial document.
1. Add x32 org part and industrial temperature part
1. change scan order(1) form 4T to 6T at 119BGA(x18)
1. Final spec release
2. Change I
SB2
form 50mA to 60mA
Draft Date
May. 18. 2001
Aug. 11. 2001
Aug. 28 .2001
Nov. 16. 2001
Remark
Preliminary
Preliminary
Preliminary
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Nov 2001
Rev 1.0
K7N803601B
K7N803201B
K7N801801B
256Kx36/x32 & 512Kx18 Pipelined NtRAM
TM
8Mb NtRAM(Flow Through / Pipelined) Ordering Information
Org.
Part Number
Mode
VDD
Speed
FT ; Access Time(ns)
Pipelined ; Cycle Time(MHz)
6.5/7.5/8.5 ns
167/133 MHz
250/225/200 MHz
167/133 MHz
250/225/200 MHz
6.5/7.5/8.5 ns
167/133 MHz
250/225/200 MHz
167/133 MHz
250/225/200 MHz
6.5/7.5/8.5 ns
167/133 MHz
250/225/200 MHz
167/133 MHz
250/225/200 MHz
Q:
100TQFP
H:
119BGA
C:
Commercial
Temperature
Range
I:
Industrial
Temperature
Range
PKG
Temp
K7M801825B-Q(H)C(I)65/75/85
K7N801801B-Q(H)C(I)16/13
512Kx18 K7N801809B-Q(H)C(I)25/22/20
K7N801845B-Q(H)C(I)16/13
K7N801849B-Q(H)C(I)25/22/20
K7M803225B-QC(I)65/75/85
K7N803201B-QC(I)16/13
256Kx32 K7N803209B-QC(I)25/22/20
K7N803245B-QC(I)C16/13
K7N803249B-QC(I)25/22/20
K7M803625B-Q(H)C(I)65/75/85
K7N803601B-Q(H)C(I)16/13
256Kx36 K7N803609B-Q(H)C(I)25/22/20
K7N803645B-Q(H)C(I)16/13
K7N803649B-Q(H)C(I)25/22/20
FlowThrough
Pipelined
Pipelined
Pipelined
Pipelined
FlowThrough
Pipelined
Pipelined
Pipelined
Pipelined
FlowThrough
Pipelined
Pipelined
Pipelined
Pipelined
3.3
3.3
3.3
2.5
2.5
3.3
3.3
3.3
2.5
2.5
3.3
3.3
3.3
2.5
2.5
-2-
Nov 2001
Rev 1.0
K7N803601B
K7N803201B
K7N801801B
256Kx36/x32 & 512Kx18 Pipelined NtRAM
TM
256Kx32 & 256Kx36 & 512Kx18-Bit Pipelined NtRAM
TM
FEATURES
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
•
Α
interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package).
• Operating in commercial and industrial temperature range.
GENERAL DESCRIPTION
The K7N803601B, K7N803201B and K7N801801B are
9,437,184 bits Synchronous Static SRAMs.
The NtRAM
TM
, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N803601B, K7N803201B and K7N801801B are imple-
mented with SAMSUNG′s high performance CMOS technology
and is available in 100pin TQFP and 119BGA packages
(100pin TQFP only for K7N803201B).
Multiple power and ground pins minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
t
CYC
t
CD
t
OE
-16
6.0
3.5
3.5
-13
7.5
4.2
3.8
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
A [0:17] or
A [0:18]
LBO
ADDRESS
REGISTER
A
2
~A
17
or A2~A18
A
0
~A
1
BURST
ADDRESS
COUNTER
A′
0
~A′
1
256Kx36/32 , 512Kx18
MEMORY
ARRAY
CLK
CKE
K
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CONTROL
LOGIC
K
DATA-IN
REGISTER
DATA-IN
REGISTER
K
CS
1
CS
2
CS
2
ADV
WE
BW
x
(x=a,b,c,d or a,b)
OE
ZZ
DQa
0
~ DQd
7
or DQa0 ~ DQb8
DQPa ~ DQPd
36/32 or 18
CONTROL
REGISTER
CONTROL
LOGIC
K
OUTPUT
REGISTER
BUFFER
NtRAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung,
and its architecture and functionalities are supported by NEC and Toshiba.
-3-
Nov 2001
Rev 1.0
K7N803601B
K7N803201B
K7N801801B
PIN CONFIGURATION
(TOP VIEW)
BWd
256Kx36/x32 & 512Kx18 Pipelined NtRAM
TM
BWb
BWa
BWc
CKE
ADV
N.C.
CLK
CS
1
CS
2
CS
2
V
DD
V
SS
WE
A
17
83
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
10
A
11
A
12
A
13
A
14
A
15
PIN NAME
SYMBOL
A
0
- A
17
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
/NC
V
DDQ
V
SSQ
PIN NAME
TQFP PIN NO.
32,33,34,35,36,37,44
45,46,47,48,49,50,81
82,83,99,100
Address Advance/Load
ADV
85
Read/Write Control Input 88
WE
CLK
Clock
89
CKE
Clock Enable
87
CS
1
Chip Select
98
CS
2
Chip Select
97
CS
2
Chip Select
92
BWx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
Output Enable
86
ZZ
Power Sleep Mode
64
LBO
Burst Mode Control
31
Power Supply(+3.3V) 14,15,16,41,65,66,91
Ground
17,40,67,90
No Connect
38,39,42,43,84
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
LBO
V
SS
Output Power Supply 4,11,20,27,54,61,70,77
(3.3V or 2.5V)
Output Ground
5,10,21,26,55,60,71,76
Notes :
1. The pin 84 is reserved for address bit for the 16Mb NtRAM.
2. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
3. DQPa~DQPd are NC for K7N803201B.
-4-
A
16
50
DQPc/NC
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
V
DD
V
DD
V
DD
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd/NC
81
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7N803601B(256Kx36)
K7N803201B(256Kx32)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
V
DD
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa/NC
Nov 2001
Rev 1.0
K7N803601B
K7N803201B
K7N801801B
PIN CONFIGURATION
(TOP VIEW)
256Kx36/x32 & 512Kx18 Pipelined NtRAM
TM
BWb
BWa
CKE
ADV
CS
2
N.C.
N.C.
N.C.
CLK
CS
1
CS
2
V
DD
V
SS
WE
A
18
83
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
11
A
12
A
13
A
14
A
15
A
16
PIN NAME
SYMBOL
A
0
- A
18
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
V
DD
V
SS
N.C.
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
TQFP PIN NO.
14,15,16,41,65,66,91
17,40,67,90
1,2,3,6,7,25,28,29,30,
38,39,42,43,51,52,53,
56,57,75,78,79,84,95,96
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
32,33,34,35,36,37,44
45,46,47,48,49,50,80
81,82,83,99,100
ADV
Address Advance/Load
85
WE
Read/Write Control Input 88
CLK
Clock
89
CKE
Clock Enable
87
CS
1
Chip Select
98
CS
2
Chip Select
97
CS
2
Chip Select
92
BWx(x=a,b) Byte Write Inputs
93,94
OE
Output Enable
86
ZZ
Power Sleep Mode
64
LBO
Burst Mode Control
31
LBO
V
SS
DQa
0
~a
8
DQb
0
~b
8
Data Inputs/Outputs
V
DDQ
V
SSQ
Output Power Supply
(3.3V or 2.5V)
Output Ground
A
17
50
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
8
DQb
7
V
SSQ
V
DDQ
DQb
6
DQb
5
V
DD
V
DD
V
DD
V
SS
DQb
4
DQb
3
V
DDQ
V
SSQ
DQb
2
DQb
1
DQb
0
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7N801801B(512Kx18)
A
10
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQa
0
DQa
1
DQa
2
V
SSQ
V
DDQ
DQa
3
DQa
4
V
SS
V
DD
V
DD
ZZ
DQa
5
DQa
6
V
DDQ
V
SSQ
DQa
7
DQa
8
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
Notes :
1. The pin 84 is reserved for address bit for the 16Mb NtRAM.
2. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-5-
Nov 2001
Rev 1.0
京公网安备 11010802033920号
EEWORLD
