P
RELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
1
Z87001/Z87L01
ROM
LESS
S
PREAD
S
PECTRUM
C
ORDLESS
P
HONE
C
ONTROLLER
FEATURES
Device
Z87001
Z87L01
ROM *
(KWords)
64
64
RAM
I/O
(Words) Lines
512
512
32
32
Package
Information
144-Pin QFP
144-Pin QFP
s
1
Note:
*Maximum accessible external ROM
s
Transceiver/Controller Chip Optimized for Implement-
ation of 900 MHz Spread Spectrum Cordless Telephone
– Adaptive Frequency Hopping
– Transmit Power Control
– Error Control Signaling
– Handset Power Management
– Support of 32 kbps ADPCM Speech Coding for
High Voice Quality
DSP Core Acts as Phone Controller
– Zilog-Provided Embedded Transceiver Software to
Control Transceiver Operation and Base Station-
Handset Communications Protocol
– User-Modifiable Software Governs Telephone
Features
Transceiver Circuitry Provides Primary Cordless Phone
Communications Functions
– Digital Downconversion with Automatic Frequency
Control (AFC) Loop
– FSK Demodulator
– FSK Modulator
– Symbol Synchronizer
–
Time Division Duplex (TDD) Transmit and Receive
Buffers
s
s
On-Chip A/D and D/A to Support 10.7 MHz IF Interface
Up to 64 Kw of External Program Memory Accessible by
the DSP Core
Bus Interface to Z87010 ADPCM Processor
Static CMOS for Low Power Consumption
3.0V to 3.6V, -20
°
C to +70
°
C, Z87L01
4.5V to 5.5V, -20
°
C to +70
°
C, Z87001
16.384 MHz Base Clock
s
s
s
s
s
GENERAL DESCRIPTION
The Z87001 /Z87L01 FHSS Cordless Telephone Trans-
ceiver/Controller is expressly designed to implement a 900
MHz frequency hopping spread spectrum cordless tele-
phone compliant with US FCC regulations for unlicensed
operation. The Z87001 and Z87L01 are distinct 5V and
3.3V versions, respectively, of the core device. For the
sake of brevity, all subsequent references to the Z87001 in
this document also apply to the Z87L01 unless specifically
noted.
The Z87001 is the ROMless version of the Z87000 Spread
Spectrum Controller IC. Specifically intended to facilitate
user specific software development, the Z87001 can ac-
cess up to 64 kwords of external program ROM.
DS96WRL0800
The Z87001 supports a specific cordless phone system
design that uses frequency hopping and digital modulation
to provide extended range, high voice quality, and low sys-
tem costs.
The Z87001 uses a Zilog 16-bit fixed-point two’s comple-
ment static CMOS Digital Signal Processor core as the
phone and RF section controller. The Z87001’s DSP core
processor further supports control of the RF section’s fre-
quency synthesizer for frequency hopping and the genera-
tion of the control messages needed to coordinate incorpo-
ration of the phone’s handset and base station. Additional
on-chip transceiver circuitry supports Frequency Shift Key-
ing modulation/demodulation and multiplexing/demulti-
1
PRELIMINARY
Z87001/Z87L01
ROMless Spread Spectrum Cordless Phone Controller
Zilog
GENERAL DESCRIPTION
(Continued)
plexing of the 32 kbps voice data and 4 kbps command
data between handset and base station. The Z87001 pro-
vides thirty-two I/O pins, including four wake-up inputs and
two CPU interrupt inputs. These programmable I/O pins al-
low a variety of user-determined phone features and board
layout configurations. Additionally, the pins may be used
so that phone features and interfaces are supported by an
optional microcontroller rather than by the Z87001’s DSP
core.
In combination with an RF section designed according to
the system specifications, Zilog’s Z87010/Z87L10 ADPCM
Processor, a standard 8-bit PCM telephone codec and
minimal additional phone circuity, the Z87001 and its em-
bedded software provide a total system solution.
Codec
Codec
Z87010
ADPCM
Processor
Z87001
Spread
Spectrum
Controller
RF Section
RF Section
Z87001
Spread
Spectrum
Controller
Z87010
ADPCM
Processor
Telephone
Line
Interface
Base Station
Handset
Figure 1. System Block Diagram of a Z87001/Z87010 Based Phone
2
PRELIMINARY
DS96WRL0800
Zilog
Z87001/Z87L01
ROMless Spread Spectrum Cordless Phone Controller
Table 1. 144 Pin QFP Pin Configuration
No
Symbol
TX
AGND
RX
AV
DD
VREF
RFEON
addr[15..0]
Function
Analog transmit IF signal
Analog ground
Analog receive IF signal
Analog power supply
Analog reference voltage for RX signal
RF on/off control
DSP core program address bus
Direction
Output
–
Input
–
–
Output
Output
1
2,141
3
4,144
5
6
7,9,11,13,15,17,19,
21,23,25,27,29,31,
136,138,140
8,12,14,16,20,22,24,
28,30,32,36,37,39,
41,44,46
10,26,43,60,77,88,
109,128
18,34,51,68,86,102,
116,131
33,35,38,40,42,45,
47,49,52,54,56,59,
61,63,66,69
48,50,53,55,57,58,
62,64,65,67,70,72,
73,75,79,80
71,74,76,78,81,83,
85,89,91,93,96,98,
100,103,105,107
82,84
87
90
92
94,95,97,99,101,
104,106,108
110
111
112
113,117,119,121,
123
114
115
118,120,122
124
125
126
127
1
P1[15..0]
General-purpose I/O port 1
Input/Output
GND
V
DD
idata[15..0]
Digital ground
Digital power supply
DSP core internal data bus
–
–
Output
P0[15..0]
General-purpose I/O port 0
Input/Output
data[15..0]
DSP core program data bus
Input
ANT[1..0]
TEST
HBSW
CLKOUT
VXDATA[7..0]
VXRDYB
eib
VXSTRB
iaddr[4..0]
VXRWB
trice
VXADD[2..0]
CODCLK
irwb
/RESETB
intenb
RF antenna diversity control
Test mode select
Handset/base mode select
Clock, ADPCM processor (16.384 MHz)
ADPCM processor data bus
ADPCM processor ready
External register data strobe
ADPCM processor data strobe
External register address bus
ADPCM processor read/write control
ROMless mode select
ADPCM processor address bus
Clock to codec (2.048 MHz)
External register read/write control
Master reset
Interrupt enable
Output
Input
Input
Output
Input
Output
Output
Input
Output
Input
Input
Input
Output
Output
Input
Input
DS96WRL0800
PRELIMINARY
5
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