P
RELIMINARY
P
RODUCT
S
PECIFICATION
1
Z86U18
USB D
EVICE
C
ONTROLLER WITH
CMOS Z86K15 MCU
FEATURES
Device
Z86U18
s
1
ROM
(KB)
4
RAM
(Bytes)
188
I/O
Lines
32
Speed
(MHz)
6
s
s
Intergrated USB Transceiver @ 1.5 Mb/sec
For Use In A Variety of Applications Including Keyboards
and Game Controllers
Programmable 8-Bit Counter/Timer,
Programmable Prescaler
with
6-Bit
USB Serial Interface Engine, Transceiver, and MCU
Intergrated for USB Function Controller
+4.0V to +5.5V Operating Range
Low Power Consumption: 60 mW @ 6 MHz
s
s
s
s
s
Five Vectored, Priority Interrupts from Five Different
Sources
On-Chip Oscillator, Which Accepts A Crystal, Ceramic
Resonator, LC or External Clock Drive (all clock speeds
@ 6 MHz)
Low System EMI Emission
HALT/STOP Modes
s
Digital Inputs CMOS Levels with Internal Pull-Up
Resistors
Four Direct Connect LED Drive Ports
Power-On Reset (POR), Hardware Watch-Dog Timer
(WDT)
s
s
s
s
GENERAL DESCRIPTION
The Z86U18 USB Controller is a member of the Z8
¨
MCU
family. The Z86U18 is characterized by a flexible I/O
scheme, an efficient register architecture, and a number of
ancillary features. It contains a dedicated USB interface
(transceiver and SIE).
For applications demanding powerful I/O capabilities, the
Z86U18 (40- and 44-pin versions) provides 32 pins dedi-
cated to application input and output. These lines are
grouped into four ports, each port consists of eight lines
and are configurable under software control to provide tim-
ing, status signals, and serial or parallel I/O ports. It also
has 2 pins to connect directly to the USB cable.
To unburden the system from coping with real-time tasks,
such as counting/timing and I/O data communications, the
Z86U18 offers an on-chip counter/timer with a large num-
ber of user-selectable modes.
The Z86U18 achieves low EMI by means of several circuit
implementations in the output drivers and clock circuitry of
the device.
With fast execution, efficient use of memory, sophisticated
interrupt, input/output bit-manipulation capabilities, and
easy hardware/software system expansion, along with low
cost and low power consumption, the Z86U18 meets the
needs of a variety of sophisticated applications (Figure 1:
Functional Block Diagram)
Notes
: All signals with a preceding front slash, "/", are ac-
tive Low. For example, B//W (WORD is active Low); /B/W
(BYTE is active Low, only).
DS97KEY0102
PRELIMINARY
1
Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
GENERAL DESCRIPTION
(Continued)
Power connections follow conventional descriptions be-
low:
Connection
Power
Ground
Circuit
V
CC
GND
Device
V
DD
V
SS
2.
Watch-Dog Timer
(WDT): WDT is also driven by the
system clock and subject to same tolerance. The
WDT can be programmed for time out value of:
WDT = POR/2
3.
EMI, 801-2 and 801-4 Compliance
: When used with
good engineering practice, this device should meet
Class B FCC with at least 10 dB of margin and comply
with the 801-2 group 4 air discharge. It shall meet 801-
4 EFT requirements in a system.
4.
XTAL
: Drive to 3-pin ceramic resonator (@ 6 MHz).
5.
XTAL In
: From ceramic resonator or crystal.
This device is based on the Z86K15 device with the follow-
ing changes or modifications:
1.
Power-On Reset
(POR): POR timing is a function of
the system clock.
POR = (3
2
* 2
16
)/f = .098
POR is in seconds and frequency in Hz. It may need
a programmable timer for warm reset (USB reset).
XTAL1
VCC
Output
4
3.3 V
VR
Input
4
VCC
GND
Port 3
V
USB
D+
D-
USB SIE
and Trans
ALU
POR
Flags
Counter/
Timers
Register
Pointer
Interrupt
Control
Register File
208 x 8-Bytes
Port 2
Port 0
Port 1
4
I/O
(Bit Programmable)
8
Open-Drain
Output
8
Input
Machine
Timing & Inst.
Control
WDT
Program
Memory
4 KB ROM
Program
Counter
Open-Drain
Output
Figure 1. Z86U18 Functional Block Diagram
2
PRELIMINARY
XTAL2
DS97KEY0102
Zilog
Z86U18
USB Device Controller with CMOS Z86K15 MCU
USB FUNCTIONAL BLOCK DESCRIPTION
The USB portion of the chip is divided into two areas, the
transceiver and the Serial Interface Engine (SIE). The
transceiver handles incoming differential signals and "sin-
gle ended zero" (SE0). It also converts output data in dig-
ital form to differential drive at the proper levels.
The SIE does all other processing on incoming and out go-
ing data. This includes signal recovery timing, bit stuffing,
validity checking, data sequencing, and handshaking to
the host. Data flow into and out of the MCU portions is pro-
cessed through eight registers mapped into Expanded
Register File Memory at locations 010 to 017.
The USB SIE handles two endpoints (control at Endpoint
0 and data into the host from Endpoint 1). All communica-
tions are at the 1.5 Mb/sec HID class data rate. Future de-
vices will handle the full 12 Mb/sec data rate.
1
Preamble
sent at full speed
Hub enables low
speed port outputs
Token sent at low speed
Hub enables low
speed port outputs
SYNC
PID
Hub Setup
SYNC
PID
ENDP . . .
EOP
Data packet sent at low speed
SYNC
PID
DATA
CRC
EOP
Preamble
sent at full speed
Hub enables low
speed port outputs
Handshake sent at low speed
Hub enables low
speed port outputs
SYNC
PID
Hub Setup
SYNC
PID
EOP
Figure 2. Data To/From K86U18
USB SUSPEND/RESUME FUNCTIONALITY
Suspend is intitiated by the host only, when it stops send-
ing start of frame signaling or start of frame keep alive
pulse.
When SIE detects the absence of start of frame signaling
from the host for more than 3 miliseconds, it sets the Sus-
pend bit in Reg7 and the Supspend Interrupt bit in Reg6
which interrupts the microcontroller. There is also an inter-
nal Suspend node that reflects the state of the Suspend bit
in Reg7. This Suspend node is used to put the tranceiver
in Suspend mode. When the microcontroller gets the Sus-
pend Interrupt, it stops all the clocks.
Resume can be initiated by host or by UC. Host initiates
Resume by sending J to K transition on D+ and D- pins.
Upon detecting J to K transition, the GFI makes Resume-
out signal active, which is used to wake the UC. Once the
UC is up, it clears the suspend bit in Reg7. UC can initiate
Resume by writing 1 to Send Resume bit in Reg7 for long-
er than 10mSec. This makes GFI to send J to K transition
on D+ and D- pins which indicates to the host the Resume
state. After 10 msec UC also clears the Suspend bit in
Reg7.
U18 EMULATIONS AND CODE DEVELOPMENT
An existing ICEBOXª Emulator has been modified by the
addition of an adaptor board. This board includes a FPGA
with the logic of the SIE, a commercial USB transceiver,
and a voltage regulator. These three functions adapt our
Z86C15/K15 to the USB world allowing the customer to
develop code to be placed into the ROM of U18s.
The ICEBOX has complete functional equivalence to the
final part including pin out to the application board. This
begins with the 40-pin DIP and covers the other pin config-
urations. Once code has been verified, it can be released
to Zilog and placed into the ROM of the Z86U18.
DS97KEY0102
PRELIMINARY
3
Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
PIN IDENTIFICATION
P36
P17
P16
P15
P14
P13
P12
P11
P10
P35
GND
P00
P01
P02
P03
P04
P05
P06
P07
P34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Z86UXX
DIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P23
P22
P21
P20
P37
P24
Test
XTALI
XTAL0
GND
P25
P26
VUSB
V
CC
D+
D-
P30
P31
P32
P33
(IN)
(OUT)
Figure 3. 40-Pin DIP Pin ConÞguration
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
7
8
9
10
11
12
13
14
15
16
17
18
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
6
4
1
42
Z86U18
PLCC/QFP
20
22
24
26
40
39
38
37
36
35
34
33
32
31
30
29
28
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
Pin assignments to be determined.
Figure 4. 44-Pin PLCC and QFP Pin Assignments
4
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
PRELIMINARY
DS97KEY0102
Zilog
Z86U18
USB Device Controller with CMOS Z86K15 MCU
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
1
28
Z86U18
SOIC
14
15
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
1
Pin assignments to be determined.
Figure 5. 28-pin SOIC Assignments
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
1
28
Z86U18
PDIP
14
15
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
Pin assignments to be determined.
Figure 6. 28-pin PDIP Assignments
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