P
RELIMINARY
P
RODUCT
S
PECIFICATION
1
Z86L70/71/75/C71
IR/L
OW
-V
OLTAGE
M
ICROCONTROLLER
FEATURES
Part
Z86L70
Z86L71
Z86L75
Z86C71
ROM
(KB)
2
8
4
8
RAM*
(Bytes)
125
237
237
237
I/O
14
16
14
16
Voltage
Ranges
2.0V to 3.9V
2.0V to 3.9V
2.0V to 3.9V
4.5V to 5.5V
–
–
s
s
s
s
1
One Programmable 16-Bit Counter/Timer with
One Capture Register
Programmable Input Glitch Filter for Pulse
Reception
Five Priority Interrupts
Low Voltage Detection and Protection
Programmable Watch-Dog/Power-On Reset Circuits
Two Independent Comparators with Programmable
Interrupt Polarity
On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC (mask option), or External Clock
Drive
Mask Selectable 200 KOhm Pull-Ups on Ports 0, 2, 3
Note:
*General-Purpose
Two Standby Modes (Typical)
– STOP - 2
µ
A
– HALT - 0.8 mA
Special Architecture to Automate Both Generation and
Reception of Complex Pulses or Signals:
– One Programmable 8-Bit Counter/Timer with Two
Capture Registers
s
s
s
s
GENERAL DESCRIPTION
The Z86L7X family of IR (Infrared)/Low-Voltage Microcon-
trollers are ROM/ROMless-based members of the Z8
®
MCU single-chip family with 237/125 bytes of internal
RAM. The differentiating factor between these devices is
the availability of RAM, ROM and package options. Offer-
ing the 3V versions (Z86LXX) with the Z86C71 gives opti-
mum performance in both the low and high voltage ranges.
Zilog's CMOS Low-Voltage Microcontrollers offer fast exe-
cution, efficient use of memory, sophisticated interrupts, in-
put/output bit manipulation capabilities, automated pulse
generation/reception, and internal key-scan pull-up resis-
tors. The Z86L7X product line offers easy hardware/soft-
ware system expansion with cost-effective and low power
consumption.
The Z86L7X architecture is based on Zilog's 8-bit micro-
controller core with an Expanded Register File to allow ac-
cess to register mapped peripherals, I/O circuits, and pow-
erful counter/timer circuitry. The Z8
®
MCU offers a flexible
I/O scheme, an efficient register and address space struc-
ture, and a number of ancillary features that are useful in
many consumer, automotive, computer peripheral, and
battery operated hand-held applications.
There are three basic address spaces available to support
a wide range of configurations: Program Memory, Register
File, and Expanded Register File. The register file is com-
posed of 256/144 bytes of RAM. It includes four I/O port
registers, 15 control and status registers and the rest are
General-Purpose registers. The Expanded Register File
consists of two additional register groups (F and D). Exter-
nal Memory is not available on 18 and 20-pin versions.
DS97LVO0500
PRELIMINARY
1-1
Z86L70/71/75/C71
IR/Low-Voltage Microcontroller
Zilog
GENERAL DESCRIPTION
(Continued)
To unburden the program from coping with such real-time
problems as generating complex waveforms or receiving
and demodulating complex waveform/pulses, the Z86L7X
family offers a new intelligent counter/timer architecture
with 8-bit and 16-bit counter/timers (Figure 1). Also includ-
ed are a large number of user-selectable modes, and two
on-board comparators to process analog signals (Figure
2).
HI16
8
LO16
8
16-Bit
T16
1 2 4
8
8
SCLK
Clock
Divider
TC16H
16
8
TC16L
And/Or
Logic
HI8
8
Input
Glitch
Filter
Edge
Detect
Circuit
8-Bit
T8
8
TC8H
8
TC8L
LO8
8
Timer 16
Timer 8/16
Timer 8
Figure 1. Counter/Timer Block Diagram
1-2
PRELIMINARY
DS97LVO0500
Zilog
Z86L70/71/75/C71
IR/Low-Voltage Microcontroller
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
T
STG
T
A
Description
Supply Voltage (*)
Storage Temp.
Oper. Ambient
Temp.
Min
-0.3
-65
°
Max
+7.0
+150
°
†
Units
V
C
C
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sec-
tions of these specifications is not implied. Exposure to ab-
solute maximum rating conditions for an extended period
may affect device reliability.
1
Notes:
* Voltage on all pins with respect to GND.
† See Ordering Information
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Figure 5).
From Output
Under T
est
I
150 pF
Figure 5. Test Load Diagram
CAPACITANCE
T
A
= 25
°
C, V
CC
= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Parameter
Input capacitance
Output capacitance
I/O capacitance
Max
12 pF
12 pF
12 pF
DS97LVO0500
PRELIMINARY
1-5
FPGA/CPLD
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