BU-6174X/6184X/6186X
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TM
ENHANCED MINIATURE ADVANCED
COMMUNICATIONS ENGINE
FEATURES
•
Fully Integrated 1553A/B Notice 2,
McAir, STANAG 3838 Interface Terminal
•
Compatible with Mini-ACE (Plus)
and ACE Generations
•
Choice of :
-
RT or BC/RT/MT In Same Footprint
- RT or BC/RT/MT with 4K RAM
- BC/RT/MT with 64K RAM, and RAM
parity
•
Choice of 5V or 3.3V Logic
•
5V Transceiver with 1760 and McAir
Compatible Options
•
Comprehensive Built-In Self-Test
DESCRIPTION
The Enhanced Miniature Advanced Communications Engine
(Enhanced Mini-ACE) family of MIL-STD-1553 terminals provide com-
plete interfaces between a host processor and a 1553 bus, and integrate
dual transceiver, protocol logic, and 4K words or 64K words of RAM.
These terminals are nearly 100% footprint and software compatible
with the previous generation Mini-ACE (Plus) terminals, and are soft-
ware compatible with the older ACE series.
They are powered by a choice of 5V or 3.3V logic. Multiprotocol sup-
port of MIL-STD-1553A/B and STANAG 3838, including versions
incorporating McAir compatible transmitters, is provided. There is a
choice of 10, 12, 16, or 20 MHz clocks. The BC/RT/MT versions with
64K words of RAM include built-in RAM parity checking.
BC features include a built-in message sequence control engine, with
a set of 20 instructions. This provides an autonomous means of
implementing multi-frame message scheduling, message retry
schemes, data double buffering, asynchronous message insertion,
and reporting to the host CPU. The Enhanced Mini-ACE incorporates
a fully autonomous built-in self-test, which provides comprehensive
testing of the internal protocol logic and/or RAM.
The RT offers the same choices of subaddress buffering as the ACE
and Mini-ACE (Plus), along with a global circular buffering option,
50% rollover interrupt for circular buffers, an interrupt status queue,
and an "Auto-boot" option to support MIL-STD-1760.
These terminals provide the same flexibility in host interface configu-
rations as the ACE/Mini-ACE, along with a reduction in the host
processor's worst case holdoff time.
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
•
Flexible Processor/Memory Interface,
with Reduced Host Wait Time
•
Choice of 10, 12, 16, or 20 MHz Clock
•
Highly Autonomous BC with
Built-In Message Sequence Control:
- Frame Scheduling
- Branching
- Asynchronous Message Insertion
- General Purpose Queue
- User-defined Interrupts
•
Advanced RT Functions
- Global Circular Buffering
- Interrupt Status Queue
- 50% Circular Buffer Rollover
Interrupts
•
Selective Message Monitor
- Selection by Address, T/R Bit,
Subaddress
- Command and Data Stacks
- 50% and 100% Stack Rollover
Interrupts
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7234
©
2000 Data Device Corporation
Data Device Corporation
www.ddc-web.com
TX/RX_A
SHARED
RAM
CH. A
TRANSCEIVER
A
DATA
BUFFERS
PROCESSOR
DATA BUS
*
TX/RX_A
DATA BUS
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
D15-D0
TX/RX_B
ADDRESS BUS
ADDRESS
BUFFERS
A15-A0
PROCESSOR
ADDRESS BUS
CH. B
TRANSCEIVER
B
2
BU-6174X/6184X/6186X
Rev. C
TX/RX_B
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
RT ADDRESS
RTAD4-RTAD0, RTADP
INCMD/MCRST
MISCELLANEOUS
CLK_IN, MSTCLR,SSFLAG/EXT_TRG,
TX-INH_A, TX-INH_B, UPADDREN
* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY
FIGURE 1. ENHANCED MINI-ACE BLOCK DIAGRAM
TABLE 1. ENHANCED MINI-ACE SERIES SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATING
Supply Voltage
!
Logic +5V or +3.3V
!
RAM +5V
!
Transceiver +5V (Note 12)
Logic
!
Voltage Input Range for +5V
Logic (BU-61XX5)
!
Voltage Input Range for +3.3V
Logic (BU-61XX3/4)
RECEIVER
Differential Input Resistance
(Notes 1-6)
Differential Input Capacitance
(Notes 1-6)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
MIN
TYP
MAX
UNITS
TABLE 1. ENHANCED MINI-ACE SERIES SPECIFICATIONS
(CONT.)
PARAMETER
MIN
TYP
MAX
UNITS
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
!
+5V (RAM for 61864(5),
Logic for BU-61XX5) (Note 12)
!
+3.3V (Logic for BU-61XX3/4)
(Note 12)
!
+5V (Ch. A, Ch. B)
Current Drain (Total Hybrid)
!
BU-61865XX-XX0
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61865X3-XX2
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61864XX-XX0
+5V (RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
!
BU-61864X3-XX2
+5V (RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
!
BU-61745XX-XX0. BU-61845XX-XX0
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61745X3-XX2. BU-61845X3-XX2
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61743XX-XX0, BU-61843XX-XX0
+5V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
!
BU-61743X3-XX2, BU-61843X3-XX2
+5V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
-0.3
-0.3
-0.3
-0.3
-0.3
6.0
6.0
7.0
6.0
6.0
V
V
V
V
V
4.5
3.0
4.75
5.0
3.3
5.0
5.5
3.6
5.25
V
V
V
2.5
5
0.200
0.860
10
kΩ
pF
Vp-p
Vpeak
180
285
390
600
mA
mA
mA
mA
TRANSMITTER
Differential Output Voltage
!
Direct Coupled Across 35
Ω,
6
Measured on Bus
!
Transformer Coupled Across
70
Ω,
Measured on Bus
18
(BU-61XXXXX-XX0,
20
BU-61XXXXX-XX2) (Note 13)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer -250
Coupled Across 70 ohms
Rise/Fall Time
100
(BU-61XXXX3,
200
BU-61XXXX4)
LOGIC
V
IH
All signals except CLK_IN
2.1
CLK_IN
0.8•Vcc
V
IL
All signals except CLK_IN
CLK_IN
Schmidt Hysteresis
All signals except CLK_IN
0.4
CLK_IN
1.0
I
IH,
I
IL
All signals except CLK_IN
I
IH
(Vcc=5.25V, V
IN
=Vcc)
-10
I
IH
(Vcc=5.25V, V
IN
=2.7V)
-350
I
IH
(Vcc=3.6V, V
IN
=Vcc)
-10
I
IH
(Vcc=3.6V, V
IN
=2.7V)
-350
I
IL
(Vcc=5.25V, V
IN
=0.4V)
-350
I
IL
(Vcc=3.6V, V
IN
=0.4V)
-350
CLK_IN
I
IH
-10
I
IL
-10
V
OH
(Vcc=4.5V, V
IH
=2.7V,
2.4
V
IL
=0.2V, I
OH
=max)
V
OH
(Vcc=3.0V, V
IH
=2.7V,
2.4
V
IL
=0.2V, I
OH
=max)
V
OL
(Vcc=4.5V, V
IH
=2.7V,
V
IL
=0.2V, I
OL
=max)
V
OL
(Vcc=3.0V, V
IH
=2.7V,
V
IL
=0.2V, I
OL
=max)
I
OL
3.4
I
OH
C
I
(Input Capacitance)
C
IO
(Bi-directional signal input
capacitance)
7
9
Vp-p
180
296
412
645
mA
mA
mA
mA
20
22
27
27
10
250
Vp-p
Vp-p
mVp-p
mV
p
120
225
330
540
40
mA
mA
mA
mA
mA
150
250
300
300
nsec
nsec
120
236
352
585
40
mA
mA
mA
mA
mA
V
V
0.7
0.2•Vcc
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
V
V
0.4
0.4
V
V
mA
mA
pF
pF
160
265
370
580
mA
mA
mA
mA
10
-50
10
-33
-50
-33
10
10
160
276
392
625
mA
mA
mA
mA
100
205
310
520
40
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
100
216
332
565
40
-3.4
50
50
Data Device Corporation
www.ddc-web.com
3
BU-6174X/6184X/6186X
Rev. C
TABLE 1. ENHANCED MINI-ACE SERIES SPECIFICATIONS
(CONT.)
PARAMETER
POWER DISSIPATION
(NOTE 14)
Total Hybrid
!
BU-61865XX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61865X3-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61864XX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61864X3-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61745XX-XX0, BU-61845XX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61745X3-XX2, BU-61845X3-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61743XX-XX0, BU-61843XX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61743X3-XX2, BU-61843X3-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Hottest Die
!
BU-61XXXXX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-61XXXX3-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
CLOCK INPUT
Frequency
!
Nominal Value
• Default Mode
• Option
• Option
• Option
!
Long Term Tolerance
• 1553A Compliance
• 1553B Compliance
MIN
TYP
MAX
UNITS
TABLE 1. ENHANCED MINI-ACE SERIES SPECIFICATIONS
(CONT.)
PARAMETER
CLOCK INPUT (CONT)
!
Short Term Tolerance, 1 second
• 1553A Compliance
• 1553B Compliance
!
Duty Cycle
1553 MESSAGE TIMING
Completion of CPU Write
(BC Start)-to-Start of Next Message
for (Non-enhanced BC Mode)
BC Intermessage Gap (Note 8)
Non-enhanced
(Mini-ACE compatible) BC mode
Enhanced BC mode (Note 9)
MIN
TYP
MAX UNITS
0.99
1.22
1.45
1.90
0.99
1.28
1.58
2.16
0.80
1.03
1.26
1.71
0.80
1.09
1.39
1.97
0.88
1.11
1.33
1.79
0.88
1.17
1.46
2.05
0.69
0.92
1.15
1.60
0.69
0.98
1.28
1.86
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
-0.001
-0.01
40
2.5
0.001
0.01
60
%
%
%
µs
9.5
10.0
to
10.5
17.5
21.5
49.5
127
4
18.
22.5
50.5
129.5
19.5
23.5
51.5
131
7
µs
µs
µs
µs
µs
µs
µs
µs
BC/RT/MT Response Timeout (Note 10)
!
18.5 nominal
!
22.5 nominal
!
50.5 nominal
!
128.0 nominal
RT Response Time
(mid-parity to mid-sync) (Note 11)
Transmitter Watchdog Timeout
THERMAL
!
Operating Case/Ball Temperature
-1XX, -4XX
-2XX, -5XX
-3XX, -8XX
!
Ceramic Flatpack / Gull Lead
Thermal Resistance, Junction-to-Case,
Hottest Die (θ
JC
)
Max Case Temperature
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10 sec.)
PHYSICAL CHARACTERISTICS
Size
Flatpack/Gull lead package
Weight
Flatpack/Gull lead package
660.5
-55
-40
0
9
+125
+85
+70
11
125
160
150
+300
°C
°C
°C
°C/W
°C
°C
°C
°C
-55
-65
1.0 X 1.0 X 0.155
(25.4 x 25.4 x 3.94)
0.6
(17)
in.
(mm)
oz
(g)
0.28
0.51
0.75
1.22
0.28
0.58
0.88
1.48
W
W
W
W
W
W
W
W
16.0
12.0
10.0
20.0
-0.01
-0.10
0.01
0.1
MHz
MHz
MHz
MHz
%
%
TABLE 1 NOTES:
Notes 1 through 6 are applicable to the Receiver Differential
Resistance and Differential Capacitance specifications:
(1)
Specifications include both transmitter and receiver (tied together
internally).
Data Device Corporation
www.ddc-web.com
4
BU-6174X/6184X/6186X
Rev. C
NOTES: (Cont’d)
(2)
Impedance parameters are specified directly between pins
TX/RX_A(B) and TX/RX_A(B) of the Enhanced Mini-ACE hybrid.
It is assumed that all power and ground inputs to the hybrid are con-
nected.
The specifications are applicable for both unpowered and powered
conditions.
The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), and referenced to hybrid
ground. Transformer must be a DDC recommended transformer or
other transformer that provides an equivalent minimum CMRR.
Typical value for minimum intermessage gap time. Under software
control, this may be lengthened to 65,535 ms - message time, in
increments of 1 µs. If ENHANCED CPU ACCESS, bit 14 of
Configuration Register #6, is set to logic "1", then host accesses
during BC Start-of-Message (SOM) and End-of-Message (EOM)
transfer sequences could have the effect of lengthening the inter-
message gap time. For each host access during an SOM or EOM
sequence, the intermessage gap time will be lengthened by 6 clock
cycles. Since there are 7 internal transfers during SOM, and 5 dur-
ing EOM, this could theoretically lengthen the intermessage gap by
up to 72 clock cycles; i.e., up to 7.2 ms with a 10 MHz clock, 6.0 µs
with a 12 MHz clock, 4.5 µs with a 16 MHz clock, or 3.6 µs with a
20 MHz clock.
For Enhanced BC mode, the typical value for intermessage gap
time is approximately 10 clock cycles longer than for the non-
enhanced BC mode. That is, an addition of 1.0 µs at 10 MHz, 833
ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.
INTRODUCTION
The BU-61740/61743/61745 RT, and BU-61840/61843/61845/
61860/61864/61865 BC/RT/MT Enhanced Mini-ACE family of
MIL-STD-1553 terminals comprise a complete integrated inter-
face between a host processor and a MIL-STD-1553 bus. All
members of the Enhanced Mini-ACE family are packaged in the
same 1.0 square inch flatpack package. The Enhanced Mini-
ACE hybrids are nearly 100% footprint and software compatible
with the previous generation Mini-ACE and Mini-ACE Plus termi-
nals, and are software compatible with the original ACE series.
The Enhanced Mini-ACE provides complete multiprotocol sup-
port of MIL-STD-1553A/B/McAir and STANAG 3838. All versions
integrate dual transceiver; along with protocol, host interface,
memory management logic; and a minimum of 4K words of
RAM. In addition, the BU-61864 and BU-61865 BC/RT/MT ter-
minals include 64K words of internal RAM, with built-in parity
checking.
The Enhanced Mini-ACEs include a 5V, voltage source trans-
ceiver for improved line driving capability, with options for MIL-
STD-1760 and McAir compatibility. As a means of reducing
power consumption, there are versions for which the logic is
powered by 3.3V, rather than 5V. To provide further flexibility, the
Enhanced Mini-ACE may operate with a choice of 10, 12, 16, or
20 MHz clock inputs.
One of the new salient features of the Enhanced Mini-ACE is its
Enhanced bus controller architecture. The Enhanced BC's high-
ly autonomous message sequence control engine provides a
means for offloading the host processor for implementing multi-
frame message scheduling, message retry schemes, data dou-
ble buffering, and asynchronous message insertion. For the pur-
pose of performing messaging to the host processor, the
Enhanced BC mode includes a General Purpose Queue, along
with user-defined interrupts.
A second major new feature of the Enhanced Mini-ACE is the
incorporation of a fully autonomous built-in self-test. This test
provides comprehensive testing of the internal protocol logic. A
separate test verifies the operation of the internal RAM. Since
the self-tests are fully autonomous, they eliminate the need for
the host to write and read stimulus and response vectors.
The Enhanced Mini-ACE RT offers the same choices of single,
double, and circular buffering for individual subaddresses as
ACE and Mini-ACE (Plus). New enhancements to the RT archi-
tecture include a global circular buffering option for multiple (or
all) receive subaddresses, a 50% rollover interrupt for circular
buffers, an interrupt status queue for logging up to 32 interrupt
events, and an option to automatically initialize to RT mode with
the Busy bit set. The interrupt status queue and 50% rollover
interrupt features are also included as improvements to the
Enhanced Mini-ACE's Monitor architecture.
To minimize board space and "glue" logic, the Enhanced Mini-
ACE terminals provide the same wide choice of host interface
configurations as the ACE and Mini-ACE (Plus). This includes
support of interfaces to 16-bit or 8-bit processors, memory or
port type interfaces, and multiplexed or non-multiplexed
5
BU-6174X/6184X/6186X
Rev. C
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) Software programmable (4 options). Includes RT-to-RT Timeout
(measured mid-parity of transmit Command Word to mid-sync of
transmitting RT Status Word).
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
(12) External 10 µF Tantalum and 0.1 µF capacitors should be located
as close as possible to Pins 20 and 72, and a 0.1 µF at pin 37. For
BU-61864 and BU-61865, there should also be a 0.1 µF at pin 26.
(13) MIL-STD-1760 requires a 20 Vp-p minimum output on the stub connection.
(14) Power dissipation specifications assume a transformer coupled
configuration with external dissipation (while transmitting) of:
0.14 watts for the active isolation transformer,
0.08 watts for the active bus coupling transformer,
0.45 watts for each of the two bus isolation resistors and
0.15 watts for each of the two bus termination resistors.
Data Device Corporation
www.ddc-web.com
FPGA/CPLD
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