Philips Semiconductors
Product specification
Triple 8-bit video ADC up to 270 Msps
CONTENTS
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.1.1
8.1.2
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.3
8.4
8.5
8.6
8.7
8.8
8.9
9
9.1
9.1.1
9.1.2
9.1.3
9.2
9.3
9.4
9.5
9.6
9.7
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
LQFP144 package
LBGA208 package
FUNCTIONAL DESCRIPTION
Power management
Standby mode
Power-down mode
Analog video input
Analog multiplexers
Activity detection
ADC
Clamp
AGC
HSOSEL, DEO and SCHCKREFO
PLL
Sync-on-green
Programmable coast
Data enable
Sync separator
3-level
I
2
C-BUS REGISTER DESCRIPTION
I
2
C-bus formats
Write 1 register
Write all registers
Read register
I
2
C-bus registers overview
Offset registers (R, G and B)
Coarse registers (R, G and B)
Fine registers (R, G and B)
SOG register
PLL control
9.8
9.9
9.10
9.11
9.12
9.13
9.14
9.15
9.16
9.17
9.18
9.19
9.20
9.21
9.22
9.23
9.24
9.25
9.26
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
16.5
17
18
19
20
TDA8754
Phase register
PLL divider registers
Horizontal sync registers
Coast register
Horizontal sync selection register
Vertical sync selection register
Clamp register
Inverter register
Output register
Output enable register 1
Output enable register 2
Clock output register
Internal oscillator register
Power management register
Read register
Version register
Sign detection register
Activity detection register 1
Activity detection register 2
LIMITING VALUES
THERMAL CHARACTERISTICS
CHARACTERISTICS
TIMING
APPLICATION INFORMATION
PACKAGE OUTLINES
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I
2
C COMPONENTS
2004 May 18
2
Philips Semiconductors
Product specification
Triple 8-bit video ADC up to 270 Msps
1
FEATURES
TDA8754
•
3.3 V power supply
•
Triple 8-bit ADC:
– 0.25 LSB differential non-linearity (DNL)
– 0.6 LSB integral non-linearity (INL).
•
Analog sampling rate from 12 Msps up to 270 Msps
•
Maximum data rate:
– Single port mode: 140 MHz
– Dual port mode: 270 MHz
– 3.3 V LV-TTL outputs.
•
PLL control via I
2
C-bus:
– 390 ps PLL jitter peak to peak at 270 MHz
– Low PLL drift with temperature (2 phase steps
maximum)
– PLL generates the ADC sampling clock which can be
locked on the line frequency from 15 kHz to 150 kHz
– Integrated PLL divider
– Programmable phase clock adjustment cells.
•
Three clamp circuits for programming a clamp code
from
−24
to +136 by steps of 1 LSB (mid-scale clamping
for YUV signal)
•
Internal generation of clamp signal
•
Three independent blanking functions
•
Input:
– 700 MHz analog bandwidth
– Two independent analog inputs selectable via
I
2
C-bus
– Analog input from 0.5 V to 1 V (p-p) to produce a
full-scale ADC input of 1 V (p-p)
– Three controllable amplifiers: gain control via I
2
C-bus
to produce full-scale peak-to-peak output with a half
LSB resolution.
•
Synchronisation:
– Frame and field detection for interlaced video signal
– Parasite synchronization pulse detection and
suppression
– Sync processing for composite sync, 3-level sync and
sync-on-green signals
– Polarity and activity detection.
3
GENERAL DESCRIPTION
The TDA8754 is a complete triple 8-bit ADC with an
integrated PLL running up to 270 Msps and analog
preprocessing functions (clamp and PGA) optimized for
capturing RGB/YUV graphic signals.
The PLL generates a pixel clock from inputs HSYNC and
COAST.
The TDA8754 offers full sync processing for
sync-on-green applications. A clamp signal may be
generated internally or provided externally.
The clamp levels, gains and other settings are controlled
via the I
2
C-bus interface.
This IC supports display resolutions up to QXGA
(2048
×
1536) at 85 Hz.
2
APPLICATIONS
•
IC control via I
2
C-bus serial interface
•
Power-down mode
•
LQFP144 and LBGA208 package:
– LBGA208 package pin to pin compatible with
TDA8756.
•
RGB/YUV high-speed digitizing
•
LCD panels drive
•
LCD projection system
•
New TV concept.
2004 May 18
3
京公网安备 11010802033920号
EEWORLD
