P
RELIMINARY
P
RODUCT
S
PECIFICATION
1
Z86C04/C08
CMOS 8-B
IT
L
OW
-C
OST
1K/2K-ROM M
ICROCONTROLLERS
FEATURES
Part
Number
Z86C04
Z86C08
ROM
(KB)
1
2
RAM* Speed
(Bytes) (MHz)
125
125
12
12
Auto Permanent
Latch
WDT
Optional
Optional
Optional
Optional
–
–
–
s
1
Permanent Watch-Dog Timer (WDT)
RC Oscillator
32 kHz Operation
Note:
* General-Purpose
s
s
s
Two Programmable 8-Bit Counter/Timers,
Each with 6-Bit Programmable Prescaler
Power-On Reset (POR) Timer
On-Chip Oscillator that Accepts RC, Crystal,
Ceramic Resonance, LC, or External Clock Drive
Clock-Free WDT Reset
Low-Power Consumption (50mw)
Fast Instruction Pointer
(1.0
µ
s @ 12 MHz)
Fourteen Digital Inputs at CMOS Levels;
Schmitt-Triggered
Software Enabled Watch-Dog Timer
Programmable Interrupt Polarity
Two Standby Modes: STOP and HALT
Low-Voltage Protection
18-Pin DIP and SOIC Packages
3.0V to 5.5V Operating Range
Available Temperature Ranges
A = –40
°
C to +125
°
C
E = –40
°
C to +105
°
C
S = 0
°
C to +70
°
C
14 Input / Output Lines
Six Vectored, Prioritized Interrupts from Six Different
Sources
Two On-Board Comparators
s
s
s
s
s
s
s
s
s
s
s
ROM Mask Options:
– Low Noise
– ROM Protect
– Auto Latch
– System Clock Driving WDT (Z86C04 only)
s
s
s
GENERAL DESCRIPTION
Zilog’s Z86C04/C08 are members of the Z8
®
MCU single-
chip microcontroller family which offer easy software/hard-
ware system expansion
.
For applications demanding powerful I/O capabilities, the
Z86C04/C08’s dedicated input and output lines are
grouped into three ports, and are configurable under soft-
ware control to provide timing, status signals, or parallel
I/O.
Two on-chip counter/timers, with a large number of user
selectable modes, off-load the system of administering
real-time tasks such as counting/timing and I/O data com-
munications. Additionally, two on-board comparators pro-
cess analog signals with a common reference voltage (Fig-
ure 1).
DS97DZ80502
PRELIMINARY
1
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
GENERAL DESCRIPTION
(Continued)
Note:
All Signals with a preceding front slash, "/", are
active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE
is active Low, only).
Power connections follow conventional descriptions be-
low:
Connection
Power
Ground
Circuit
V
CC
Device
V
DD
V
SS
GND
Input
Vcc
GND
XTAL
Port 3
Machine
Timing & Inst.
Control
Counter/
Timers (2)
ALU
Interrupt
Control
FLAG
Prg. Memory
Register
Pointer
Register File
Program
Counter
Two Analog
Comparators
Port 2
Port 0
I/O
(Bit Programmable)
I/O
Figure 1. Z86C04/C08
Functional Block Diagram
2
PRELIMINARY
DS97DZ80502
Zilog
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
PIN DESCRIPTIONS
Table 1: 18-Pin DIP and SOIC Pin Identification
P24
P25
P26
P27
VCC
XTAL2
XTAL1
P31
P32
1
2
3
4
5
6
7
8
9
DIP
18
17
16
15
14
13
12
11
10
P23
P22
P21
P20
GND
P02
P01
P00
P33
Pin #
1-4
5
6
7
8
9
10
11-13
14
15-18
Symbol
P24-P27
V
CC
XTAL2
XTAL1
P31
P32
P33
P00-P02
GND
P20-P23
Function
Port 2, Pins 4, 5, 6, 7
Power Supply
Crystal Oscillator Clock
Crystal Oscillator Clock
Port 3, Pin 1, AN1
Port 3, Pin 2, AN2
Port 3, Pin 3, REF
Port 0, Pins 0, 1, 2
Ground
Port 2, Pins 0, 1, 2, 3
Direction
In/Output
Output
Input
Input
Input
Input
In/Output
In/Output
1
Figure 2. 18-Pin DIP Configuration
P24
P25
P26
P27
Vcc
XTAL2
XTAL1
P31
P32
1
2
3
4
5
6
7
8
9
18
17
16
15
P23
P22
P21
P20
GND
P02
P01
P00
P33
SOIC
14
13
12
11
10
Figure 3. 18-Pin SOIC Pin Configuration
DS97DZ80502
PRELIMINARY
3
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin with Respect to V
SS
[Note 1]
Voltage on V
DD
Pin with Respect to V
SS
Voltage on Pin 7 with Respect to V
SS
[Note 2]
Total Power Dissipation
Maximum Current out of V
SS
Maximum Current into V
DD
Maximum Current into an Input Pin [Note 3]
Maximum Current into an Open-Drain Pin [Note 4]
Maximum Output Current Sinked by Any I/O Pin
Maximum Output Current Sourced by Any I/O Pin
Total Maximum Output Current Sinked by Port 2
Total Maximum Output Current Sourced by Port 2
–600
–600
Min
–40
–65
–0.7
–0.3
–0.7
Max
+105
+150
+12
+7
V
DD
+1
462
84
84
+600
+600
12
12
70
70
Units
C
C
V
V
V
mW
mA
mA
µ
A
µ
A
mA
mA
mA
mA
Notes:
1. This applies to all pins except where otherwise noted. Maximum current into pin must be
±
600
µ
A.
2. There is no input protection diode from pin to V
DD
.
3. This excludes Pin 6 and Pin 7.
4. Device pin is not at an output Low state.
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; functional operation of the
device at any condition above those indicated in the oper-
ational sections of these specifications is not implied. Ex-
posure to absolute maximum rating conditions for an ex-
tended period may affect device reliability. Total power
dissipation should not exceed 462 mW for the package.
Power dissipation is calculated as follows:
Total Power dissipation = V
DD
x [I
DD
– (sum of I
OH
)] + sum of
[(V
DD
– V
OH
) x I
OH
] + sum of (V
0L
x I
0L
).
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin
(Figure 4).
From Output
Under T
est
150 pF
Figure 4. Test Load Diagram
4
PRELIMINARY
DS97DZ80502
Zilog
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
CAPACITANCE
T
A
= 25
°
C, V
CC
= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Parameter
Input capacitance
Output capacitance
I/O capacitance
Min
0
0
0
Max
15 pF
20 pF
25 pF
1
DC ELECTRICAL CHARACTERISTICS
T
A
= –40
°
C
to +125
°
C
Sym
V
CH
Parameter
Clock Input High
Voltage
V
CC
[4]
3.0V
5.5V
Min
0.8 V
CC
0.8 V
CC
V
SS
–0.3
V
SS
–0.3
0.7 V
CC
0.7 V
CC
V
SS
–0.3
V
SS
–0.3
V
CC
–0.4
V
CC
–0.4
V
CC
–0.4
V
CC
–0.4
Max
V
CC
+0.3
V
CC
+0.3
0.2 V
CC
0.2 V
CC
V
CC
+0.3
V
CC
+0.3
0.2 V
CC
0.2 V
CC
Typical
@ 25
°
C
1.7
2.8
0.8
1.7
1.8
2.8
0.8
1.5
3.0
4.8
3.0
4.8
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mV
mV
V
µA
µA
µA
µA
Conditions
Driven by External
Clock Generator
Driven by External
Clock Generator
Driven by External
Clock Generator
Driven by External
Clock Generator
Notes
V
CL
Clock Input Low
Voltage
3.0V
5.5V
V
IH
V
IL
V
OH
Input High Voltage
Input Low Voltage
Output High
Voltage
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
1
1
1
1
I
OH
= –2.0 mA
I
OH
= –2.0 mA
Low Noise @ I
OH
= –0.5 mA
Low Noise @ I
OH
= –0.5 mA
I
OL
= +4.0 mA
I
OL
= +4.0 mA
Low Noise @ I
OL
= 1.0 mA
Low Noise @ I
OL
= 1.0 mA
I
OL
= +12 mA
I
OL
= +12 mA
5
5
5
5
5
5
V
OL1
Output Low Voltage
3.0V
5.5V
3.0V
5.5V
0.8
0.6
0.6
0.6
1.2
1.0
25
25
3.0
1.0
1.0
1.0
1.0
0.2
0.1
0.2
0.1
0.8
0.3
10
10
2.6
V
OL2
V
OFFSET
V
LV
I
IL
Output Low Voltage
Comparator Input
Offset Voltage
V
CC
Low Voltage
Auto Reset
Input Leakage
(Input Bias
Current of
Comparator)
Output Leakage
3.0V
5.5V
3.0V
5.5V
1.8
3.0V
5.5
3.0V
5.5V
–1.0
–1.0
–1.0
–1.0
Int. CLK Freq @ 2 MHz Max.
V
IN
= 0V, V
CC
V
IN
= 0V, V
CC
V
IN
= 0V, V
CC
V
IN
= 0V, Vcc
I
OL
DS97DZ80502
PRELIMINARY
5
京公网安备 11010802033920号
EEWORLD
