EEWORLDEEWORLDEEWORLD

Part Number

Search

DCPO37S3HLF

Description
D Subminiature Connector, 37 Contact(s), Female, Solder Terminal, LEAD FREE
CategoryThe connector    The connector   
File Size175KB,1 Pages
ManufacturerAmphenol
Websitehttp://www.amphenol.com/
Environmental Compliance  
Download Datasheet Parametric View All

DCPO37S3HLF Overview

D Subminiature Connector, 37 Contact(s), Female, Solder Terminal, LEAD FREE

DCPO37S3HLF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerAmphenol
package instructionLEAD FREE
Reach Compliance Codecompliant
Connector typeD SUBMINIATURE CONNECTOR
Contact to complete cooperationGOLD (8) OVER NICKEL
Contact completed and terminatedGOLD (8) OVER NICKEL
Contact point genderFEMALE
Contact materialCOPPER ALLOY
DIN complianceNO
empty shellNO
Filter functionNO
IEC complianceNO
insulator materialPOLYETHYLENE
JESD-609 codee4
MIL complianceNO
Manufacturer's serial numberDP
Plug informationMULTIPLE MATING PARTS AVAILABLE
Mixed contactsNO
Installation typeBOARD AND PANEL
OptionsGENERAL PURPOSE
Shell surfaceZINC
Shell materialSTEEL
Housing size4/C
Termination typeSOLDER
Total number of contacts37
UL Flammability Code94V-0
C-DSUB-0067
6
PDM: Rev:F
STATUS:
Released
Printed: Mar 27, 2008
.
LC Oscillator Circuit Analysis
[backcolor=rgb(239, 245, 249)][size=14px]The purpose of the circuit should be to generate a small sinusoidal current on the collector of Q2, and then output it to the next stage of transistor/op amp f...
jplzl10000 Analog electronics
Equivalent circuit diagram of analog filter
Can the analog filters we often talk about be equivalent to series or parallel circuits of capacitors and inductors?...
secondlife110 RF/Wirelessly
How to stop WINCE from booting?
I got a board from my friend. There is already a program on his board. The program runs automatically as soon as the computer is turned on, and runs in full screen. I can't exit the program no matter ...
神童一休 Embedded System
Xilinx FPGA Design Advanced (Advanced Edition)
...
至芯科技FPGA大牛 FPGA/CPLD
About the update of Verilog state machine
I have just started to learn FPGA, and I would like to ask a question about state machine from Verilog master. A common way to write state machine in Verilog is always @(posedge clk, negedge reset) be...
liluchang1993 FPGA/CPLD
A fresh start
[i=s]This post was last edited by paulhyde on 2014-9-15 04:11[/i] [i=s]This post was last edited by paulhyde on 2014-9-15 04:11[/i] Come on!...
琴箫雨霁 Electronics Design Contest

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1067  1579  307  1974  2248  22  32  7  40  46 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号