HM658512AI Series
4 M PSRAM (512-kword
×
8-bit)
2 k Refresh
ADE-203-286C(Z)
Rev. 3.0
March 15, 1999
Description
The Hitachi HM658512AI is a 4-Mbit pseudo static RAM organized 524288-word
×
8-bit. It realizes
higher density, higher performance and low power consumption by employing 0.8
µm
Hi-CMOS process
technology. It offers low power data retention by self refresh mode. HM658512AI is suitable for handy
systems which work with battery back-up systems. It is packaged in 32-pin plastic SOP.
Features
•
Single 5 V supply: 5 V
±10%
•
High speed
CE
access time: 80 ns/100 ns/120 ns (max)
Random read/write cycle time: 130 ns/160 ns/190 ns (min)
•
Power dissipation
Active: 250 mW (typ)
Standby: 350
µW
(typ)
•
Directly TTL compatible all inputs and outputs
•
Simple address configuration
Non multiplexed address
•
Refresh cycle
2048 refresh cycles: 32 ms
•
Easy refresh functions
Address refresh
Automatic refresh
Self refresh
•
Temperature range: –40 to +85°C
HM658512AI Series
Block Diagram
A0
Address
latch
control
Row
decoder
Memory matrix
(2048
×
256)
×
8
A10
Column I/O
Column decoder
Address latch control
I/O 0
I/O 7
Input
data
control
A11
A18
Refresh
control
CE
OE/RFSH
WE
Timing pulse generator
Read write control
Pin Functions
CE
(Input) :
CE
is a basic clock. RAM is active when
CE
is low, and is on standby when
CE
is high.
A0 to A18 (Input):
A0 to A10 are row addresses and A11 to A18 are column addresses. The entire
addresses A0 to A18 are fetched into RAM by the falling edge of
CE.
OE/RFSH
(Input) :
This pin has two functions. Basically it works as
OE
when
CE
is low, and as
RFSH
when
CE
is high (in standby mode). After a read or write cycle finishes, refresh does not start if
CE
goes
high while
OE/RFSH
is held low. In order to start a refresh in standby mode,
OE/RFSH
must go high to
reset the refresh circuits of the RAM. After the refresh circuits are reset, the refresh starts when
OE/RFSH
goes low.
I/O0 to I/O7 (Inputs and Outputs) :
These pins are data I/O pins.
WE(Input):
RAM is in write mode when
WE
is low, and is in read mode when
WE
is high. I/O data is
fetched into RAM by the rising edge of
WE
or
C E
(earlier timing) and the data is written into memory
cells.
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HM658512AI Series
Notes
Refresh
There are three refresh modes : address refresh, automatic refresh and self refresh.
(1) Address refresh: Data is refreshed by accessing all 2048 row addresses every 32 ms. A read is one
method of accessing those addresses. Each row address (2048 addresses of A0 to A10)must be read at
least once every 32 ms. In address refresh mode,
OE/RFSH
can remain high. In this case, the I/O pins
remain at high impedance, but the refresh is done within RAM.
(2) Automatic refresh: Instead of address refresh, automatic refresh can be used. RAM goes to automatic
refresh mode if
OE/RFSH
falls while
CE
is high and it remains low for at least t
FAP
. One automatic
refresh cycle is executed by one low pulse of
OE/RFSH.
It is not necessary to input the refresh
address from outside since it is generated internally by an on-chip address counter. 2048 automatic
refresh cycles must be done every 32 ms.
(3) Self refresh: Self refresh mode is suitable for data retention by battery. In standby mode, a self refresh
starts automatically when
OE/RFSH
stays low for more than 8
µs.
Refresh addresses are automatically
specified by the on-chip address counter, and the refresh period is determined by the on-chip timer.
Automatic refresh and self refresh are distinguished from each other by the width of the
OE/RFSH
low
pulse in standby mode. If the
OE/RFSH
low pulse is wider than 8
µs,
RAM becomes into self refresh
mode; if the
OE/RFSH
low pulse is less than 8
µs,
it is recognized as an automatic refresh instruction.
At the end of self refresh, refresh reset time (t
RFS
) is required to reset the internal self refresh operation of
the RAM. During t
RFS
,
CE
and
OE/RFSH
must be kept high. If auto refresh follows self refresh, low
transition of
OE/RFSH
at the beginning of automatic refresh must not occur during t
RFS
period.
Others
Since pseudo static RAM consists of dynamic circuits like DRAM, its clock pins are more noise-sensitive
than conventional SRAM’s.
(1) If a short
CE
pulse of a width less than t
CE
min is applied to RAM, an incomplete read occurs and
stored data may be destroyed. Make sure that
CE
low pulses of less than t
CE
min are inhibited. Note
that a 10 ns
CE
low pulse may sometimes occur owing to the gate delay on the board if the
CE
signal is
generated by the decoding of higher address signals on the board. Avoid these short pulses.
(2)
OE/RFSH
works as refresh control in standby mode. A short
OE/RFSH
low pulse may cause an
incomplete refresh that will destroy data. Make sure that
OE/RFSH
low pulse of less than t
FAP
min are
also inhibited.
(3) t
OHC
and t
OCD
are the timing specs which distinguish the
OE
function of
OE/RFSH
from the
RFSH
function. The t
OHC
and t
OCD
specs must be strictly maintained.
(4) Start the HM658512AI operating by executing at least eight initial cycles (dummy cycles) at least 100
µs
after the power voltage reaches 4.5 V to 5.5 V after power-on.
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RF/Wirelessly
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