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MC100LVEL92
5V Triple PECL Input to
LVPECL Output Translator
Description
The MC100LVEL92 is a triple PECL input to LVPECL output
translator. The device receives standard PECL signals and translates
them to differential LVPECL output signals.
To accomplish the PECL to LVPECL level translation, the
MC100LVEL92 requires three power rails. The V
CC
supply is to be
connected to the standard 5 V PECL supply, the LV
CC
supply is to be
connected to the 3.3 V LVPECL supply, and Ground is connected to
the system ground plane. Both the V
CC
and LV
CC
should be bypassed
to ground with 0.01
mF
capacitors.
The PECL V
BB
pin, an internally generated voltage supply, is
available to this device only. For single-ended input conditions, the
unused differential input is connected to V
BB
as a switching reference
voltage. V
BB
may also rebias AC coupled inputs. When used,
decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current
sourcing or sinking to 0.5 mA. When not used, V
BB
should be
left open.
Features
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SO−20 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
100LVEL92
AWLYYWWG
•
500 ps Propagation Delays
•
5 V and 3.3 V Supplies Required
•
ESD Protection: Human Body Model; >2 kV,
•
•
•
•
•
•
•
•
•
•
Machine Model; >200 V
The 100 Series Contains Temperature Compensation
LVPECL Operating Range: LV
CC
= 3.0 V to 3.8 V
PECL Operating Range: V
CC
= 4.5 V to 5.5 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or < GND + 1.3 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Pb = Level 1
Pb−Free = Level 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index 28 to 34
Transistor Count = 247 devices
Pb−Free Packages are Available*
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2008
November, 2008
−
Rev. 12
1
Publication Order Number:
MC100LVEL92/D
MC100LVEL92
V
CC
20
Q0
19
Q0 LV
CC
18
17
Q1
16
Q1
15
LV
CC
Q2
14
13
Q2
12
V
CC
11
Table 1. PIN DESCRIPTION
PIN
Dn, Dn
Qn, Qn
PECL V
BB
LV
CC
V
CC
GND
FUNCTION
PECL Inputs
LVPECL Outputs
PECL Reference Voltage Output
LVPECL Power Supply
PECL Power Supply
Common Ground Rail
LVPECL
LVPECL
LVPECL
PECL
PECL
PECL
1
V
CC
2
D0
3
D0
4
V
BB
PECL
5
D1
6
D1
7
V
BB
PECL
8
D2
9
D2
10
GND
Warning: All V
CC
, LV
CC
, and GND pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout: SO−20 WB
(Top View)
Table 2. MAXIMUM RATINGS
Symbol
V
CC
LV
CC
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
PECL Power Supply
LVPECL Power Supply
PECL Input Voltage
Output Current
PECL V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
Standard Board
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
SOIC−20 WB
SOIC−20 WB
SOIC−20 WB
Condition 1
GND = 0 V
GND = 0 V
GND = 0 V
Continuous
Surge
V
I
V
CC
Condition 2
Rating
8 to 0
8 to 0
6 to 0
50
100
±
0.5
−40
to +85
−65
to +150
90
60
30 to 35
265
265
Unit
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may
affect device reliability.
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2
MC100LVEL92
Table 3. PECL INPUT DC CHARACTERISTICS
V
CC
= 5.0 V; LV
CC
= 3.3 V; GND = 0 V Note 1)
−40°C
Symbol
IV
CC
V
IH
V
IL
PECL V
BB
V
IHCMR
Characteristic
PECL Power Supply Current
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (DIfferential) (Note 2)
V
pp
< 500 mV
V
pp
y
500 mV
Input HIGH Current
Input LOW Current
D
D
0.5
−600
3835
3190
3.62
Min
Typ
Max
12
4120
3515
3.74
3835
3190
3.62
Min
25°C
Typ
Max
12
4120
3525
3.74
3835
3190
3.62
Min
85°C
Typ
Max
12
4120
3525
3.74
Unit
mA
mV
mV
V
1.3
1.5
4.8
4.8
150
1.2
1.4
4.8
4.8
150
1.2
1.4
4.8
4.8
150
V
V
mA
mA
I
IH
I
IL
0.5
−600
0.5
−600
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input parameters vary 1:1 with V
CC
. V
CC
can vary 4.5 V to 5.5 V.
2. V
IHCMR
min varies 1:1 with GND. V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min
and 1.0 V.
Table 4. LVPECL OUTPUT DC CHARACTERISTICS
V
CC
= 5.0 V; LV
CC
= 3.3 V; GND = 0 V (Note 3)
−40°C
Symbol
ILV
CC
V
OH
V
OL
Characteristic
LVPECL Power Supply Current
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
2215
1470
2295
1605
Min
Typ
Max
20
2420
1745
2275
1490
2345
1595
Min
25°C
Typ
Max
20
2420
1680
2275
1490
2345
1595
Min
85°C
Typ
Max
21
2420
1680
Unit
mA
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Output parameters vary 1:1 with LV
CC
. V
CC
can vary 3.0 V to 3.8 V.
4. Outputs are terminated through a 50
W
resistor to LV
CC
−
2.0 V.
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3
MC100LVEL92
Table 5. AC CHARACTERISTICS
V
CC
= 5.0 V; LV
CC
= 3.3 V; GND = 0 V (Note 5)
−40°C
Symbol
f
max
t
PLH
t
PHL
t
SKEW
Characteristic
Maximum Toggle Frequency
Propagation Delay
D to Q
Skew
Diff
S.E.
490
440
Min
Typ
TBD
590
590
20
20
25
TBD
150
270
1000
530
150
270
690
740
100
200
510
460
Max
Min
25°C
Typ
TBD
610
610
20
20
25
TBD
1000
530
150
270
710
760
100
200
530
480
Max
Min
85°C
Typ
TBD
630
630
20
20
25
TBD
1000
530
730
780
100
200
Max
Unit
GHz
ps
ps
Output−to−Output (Note 6)
Part−to−Part (Diff) (Note 6)
Duty Cycle (Diff) (Note 7)
t
JITTER
V
PP
t
r
t
f
Cycle−to−Cycle Jitter
Input Swing (Note 8)
Output Rise/Fall Times Q
(20%
−
80%)
ps
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. LV
CC
can vary 3.0 V to 3.8 V; V
CC
can vary 4.5 V to 5.5 V. Outputs are terminated through a 50
W
resistor to LV
CC
−
2.0 V.
6. Skews are valid across specified voltage range, part−to−part skew is for a given temperature.
7. Duty cycle skew is the difference between a t
PLH
and t
PHL
propagation delay through a device.
8. V
PP
(min) is the minimum input swing for which AC parameters are guaranteed. The device has a DC gain of
≈40.
Q
Driver
Device
Q
Z
o
= 50
W
D
Receiver
Device
Z
o
= 50
W
50
W
50
W
D
V
TT
V
TT
= V
CC
−
2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D
−
Termination of ECL Logic Devices.)
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