Data Sheet
ZL40264
Four output ultra-low additive phase noise PCIe Gen 1 to 5,
and UPI/QPI fanout buffer
Features
•
One differential input which accepts any
differential format.
•
Four differential HCSL outputs
•
Ultra-low additive jitter: 32fs (in 12kHz to 20MHz
integration band at 400MHz clock frequency)
•
Supports clock frequencies from 0 to 400MHz
•
Supports 2.5V or 3.3V power supplies for HCSL
outputs
•
Embedded Low Drop Out (LDO) Voltage regulator
provides superior Power Supply Noise Rejection
•
Maximum output to output skew of 50ps
•
Individual Output Enable pin for each differential
pair.
•
Transfers Spread-Spectrum without attenuation
ZL40264LDG1
ZL40264LDF1
Ordering Information
20 pin QFN
20 pin QFN
Trays
Tape and Reel
Package size: 4 x 4 mm
-40
C to +85
C
Applications
•
•
•
•
•
•
•
PCI Express generation 1/2/3/4/5 clock distribution
UPI/QPI clock distribution
Low jitter clock trees
Logic translation
Clock and data signal restoration
High performance microprocessor clock distribution
Test Equipment
OE[3:0]_b
OUT0_p
OUT0_n
OUT1_p
OUT1_n
OUT2_p
OUT2_n
IN_p
IN_n
ZL40264
OUT3_p
OUT3_n
Figure 1. Functional Block Diagram
June 2019
© 2019 Microsemi Corporation
ZL40264
1
Data Sheet
ZL40264
Table of Contents
Features ..................................................................................................................................... 1
Applications................................................................................................................................ 1
Table of Contents ...................................................................................................................... 2
Pin Diagram ............................................................................................................................... 5
Pin Descriptions ......................................................................................................................... 6
Functional Description ............................................................................................................... 7
Clock Inputs ............................................................................................................................... 7
Clock Outputs .......................................................................................................................... 10
Termination of unused outputs ................................................................................................ 11
Power Consumption ................................................................................................................ 11
Power Supply Filtering ............................................................................................................. 11
Power Supplies and Power-up Sequence ............................................................................... 12
Device Control ......................................................................................................................... 12
Typical phase noise performance ............................................................................................ 13
AC and DC Electrical Characteristics ...................................................................................... 14
Absolute Maximum Ratings ..................................................................................................... 14
Recommended Operating Conditions ..................................................................................... 14
Package Outline ...................................................................................................................... 24
Change history: ........................................................................................................................ 25
June 2019
© 2019 Microsemi Corporation
ZL40264
2
Data Sheet
ZL40264
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Functional Block Diagram ........................................................................................................................................... 1
Pin Diagram ................................................................................................................................................................ 5
Input driven by source terminated HCSL ..................................................................................................................... 7
Input driven by receiver terminated HCSL .................................................................................................................. 8
Input driven by AC coupled LVPECL output ................................................................................................................. 8
Input driven by AC coupled LVDS ................................................................................................................................ 8
Input driven by a single ended output ........................................................................................................................ 9
Source terminated HCSL ........................................................................................................................................... 10
Receiver terminated HCSL......................................................................................................................................... 10
Power Supply Filtering .............................................................................................................................................. 12
100MHz HCSL Phase Noise ...................................................................................................................................... 13
133MHz HCSL Phase Noise ....................................................................................................................................... 13
400MHz HCSL Phase Noise ....................................................................................................................................... 13
Single-Ended Measurement Points for Absolute Cross Point and Swing .................................................................. 21
Single-Ended Measurement Points for Delta Cross Point ......................................................................................... 21
Single-Ended Measurement Points for Rise and Fall Time Matching ....................................................................... 21
Differential Measurement Points for Rise and Fall Time .......................................................................................... 22
Differential Measurement Points for Ringback ........................................................................................................ 22
Test Circuit ................................................................................................................................................................ 22
June 2019
© 2019 Microsemi Corporation
ZL40264
3
Data Sheet
ZL40264
List of Tables
Table 1 Pin Descriptions ................................................................................................................................................................................. 6
Table 2 Absolute Maximum Ratings* ........................................................................................................................................................... 14
Table 3 Recommended Operating Conditions* ............................................................................................................................................ 14
Table 4 Current consumption ....................................................................................................................................................................... 15
Table 5 Input Characteristics* ...................................................................................................................................................................... 15
Table 6 Power Supply Rejection Ratio for VDD = VDDO = 3.3V* .................................................................................................................. 15
Table 7 Power Supply Rejection Ratio for VDD = VDDO = 2.5V* .................................................................................................................. 16
Table 8 HCSL Outputs for VDDO = 3.3V* ...................................................................................................................................................... 17
Table 9 HCSL (PCIe) Jitter Performance for VDDO = 3.3V ............................................................................................................................. 18
Table 10 HCSL Outputs for VDDO = 2.5V* .................................................................................................................................................... 19
Table 11 HCSL (PCIe) Jitter Performance for VDDO = 2.5V ........................................................................................................................... 20
Table 12 4x4mm QFN Package Thermal Properties ..................................................................................................................................... 23
June 2019
© 2019 Microsemi Corporation
ZL40264
4
Data Sheet
ZL40264
Pin Diagram
The device is packaged in a 4x4mm 20-pin QFN.
Pin#1
Corner
IN_p
20
19
OE0_b
IN_n
18
17
VDD
1
OUT0_n
16
OUT0_p
15
VDDO
GND
2
14
GND
OE3_b
3
Exposed GND Pad 2.125 x 2.125 mm
13
OE1_b
OUT3_n
4
12
OUT1_p
OUT3_p
5
11
OUT1_n
6
7
8
9
10
VDDO
OUT2_n
OUT2_p
Figure 2. Pin Diagram
June 2019
© 2019 Microsemi Corporation
ZL40264
OE2_b
GND
5
京公网安备 11010802033920号
EEWORLD
