DM9010
Single Chip Ethernet Controller with General Processor Interface
DAVICOM Semiconductor, Inc.
DM9010
10/100 Mbps Single Chip Ethernet Controller
with General Processor Interface
DATA SHEET
Preliminary
Version: DM9010-17 -DS-P04
Jan. 18. 2006
Preliminary
Version: DM9010-17--DS-P04
Jan. 18, 2006
1
DM9010
Single Chip Ethernet Controller with General Processor Interface
Content
1. GENERAL DESCRIPTION.............................................................................................................................................. 7
2. BLOCK DIAGRAM........................................................................................................................................................... 7
3. FEATURES......................................................................................................................................................................... 8
4. PIN CONFIGURATION ................................................................................................................................................... 9
4.1 P
IN
C
ONFIGURATION
I:
WITH
MII I
NTERFACE
................................................................................................................. 9
4.2 P
IN
C
ONFIGURATION
II:
WITH
32-B
IT
D
ATA
B
US
......................................................................................................... 10
5. PIN DESCRIPTION......................................................................................................................................................... 11
5.1 MII I
NTERFACE
............................................................................................................................................................. 11
5.2 P
ROCESSOR
I
NTERFACE
................................................................................................................................................ 11
5.3 EEPROM I
NTERFACE
................................................................................................................................................... 12
5.4 C
LOCK
I
NTERFACE
........................................................................................................................................................ 13
5.5 LED I
NTERFACE
........................................................................................................................................................... 13
5.6 10/100 PHY/F
IBER
....................................................................................................................................................... 13
5.7 M
ISCELLANEOUS
.......................................................................................................................................................... 14
5.8 P
OWER
P
INS
.................................................................................................................................................................. 14
5.9
STRAP PINS TABLE
......................................................................................................................................................... 14
6. VENDOR CONTROL AND STATUS REGISTER SET.............................................................................................. 15
6.1 N
ETWORK
C
ONTROL
R
EGISTER
(00H).......................................................................................................................... 17
6.2 N
ETWORK
S
TATUS
R
EGISTER
(01H) ............................................................................................................................. 17
6.3 TX C
ONTROL
R
EGISTER
(02H) ..................................................................................................................................... 17
6.4 TX S
TATUS
R
EGISTER
I ( 03H )
FOR PACKET INDEX
I.................................................................................................... 18
6.5 TX S
TATUS
R
EGISTER
II ( 04H )
FOR PACKET INDEX
I I ................................................................................................ 18
6.6 RX C
ONTROL
R
EGISTER
( 05H ) ................................................................................................................................... 18
6.7 RX S
TATUS
R
EGISTER
( 06H ) ...................................................................................................................................... 19
6.8 R
ECEIVE
O
VERFLOW
C
OUNTER
R
EGISTER
( 07H )........................................................................................................ 19
6.9 B
ACK
P
RESSURE
T
HRESHOLD
R
EGISTER
(08H) ............................................................................................................ 19
6.10 F
LOW
C
ONTROL
T
HRESHOLD
R
EGISTER
( 09H ) ......................................................................................................... 20
6.11 RX/TX F
LOW
C
ONTROL
R
EGISTER
( 0AH )................................................................................................................ 20
6.12 EEPROM & PHY C
ONTROL
R
EGISTER
( 0BH ) ......................................................................................................... 21
Preliminary
Version: DM9010-17--DS-P04
Jan. 18, 2006
2
DM9010
Single Chip Ethernet Controller with General Processor Interface
6.13 EEPROM & PHY A
DDRESS
R
EGISTER
( 0CH ).......................................................................................................... 21
6.14 EEPROM & PHY D
ATA
R
EGISTER
(EE_PHY_L:0DH
EE_PHY_H:0EH) ...................................................... 21
6.15 W
AKE
U
P
C
ONTROL
R
EGISTER
( 0FH )....................................................................................................................... 21
6.16 P
HYSICAL
A
DDRESS
R
EGISTER
( 10H~15H ) .............................................................................................................. 22
6.17 M
ULTICAST
A
DDRESS
R
EGISTER
( 16H~1DH ) .......................................................................................................... 22
6.18 G
ENERAL PURPOSE CONTROL
R
EGISTER
( 1EH ) ...................................................................................................... 22
6.19 G
ENERAL PURPOSE
R
EGISTER
( 1FH )......................................................................................................................... 22
6.20 TX SRAM R
EAD
P
OINTER
A
DDRESS
R
EGISTER
(22H~23H)...................................................................................... 23
6.21 RX SRAM W
RITE
P
OINTER
A
DDRESS
R
EGISTER
(24H~25H) .................................................................................... 23
6.22 V
ENDOR
ID R
EGISTER
(28H~29H)............................................................................................................................. 23
6.23 P
RODUCT
ID R
EGISTER
(2AH~2BH).......................................................................................................................... 23
6.24 C
HIP
R
EVISION
R
EGISTER
(2CH) ................................................................................................................................ 23
6.25 T
RANSMIT
C
ONTROL
R
EGISTER
2 ( 2DH ) .................................................................................................................. 23
6.26 O
PERATION
T
EST
C
ONTROL
R
EGISTER
( 2EH )........................................................................................................... 24
6.27 S
PECIAL
M
ODE
C
ONTROL
R
EGISTER
( 2FH ) .............................................................................................................. 24
6.28 E
ARLY
T
RANSMIT
C
ONTROL
/S
TATUS
R
EGISTER
( 30H )............................................................................................. 24
6.29 T
RANSMIT
C
HECK
S
UM
C
ONTROL
R
EGISTER
( 31H ).................................................................................................. 25
6.30 R
ECEIVE
C
HECK
S
UM
C
ONTROL
S
TATUS
R
EGISTER
( 32H ) ....................................................................................... 25
6.31 E
XTERNAL
PHY
CEIVER
A
DDRESS
R
EGISTER
( 33H ) ............................................................................................... 25
6.32 G
ENERAL
P
URPOSE
C
ONTROL
R
EGISTER
2 ( 34H ) ................................................................................................... 25
6.33 G
ENERAL
P
URPOSE
R
EGISTER
2 ( 35H )............................................................................................................... 26
6.34 G
ENERAL
P
URPOSE
C
ONTROL
R
EGISTER
3 ( 36H ) ................................................................................................... 26
6.35 G
ENERAL
P
URPOSE
R
EGISTER
3 ( 37H )............................................................................................................... 26
6.36 P
ROCESSOR
B
US
C
ONTROL
R
EGISTER
( 38H )............................................................................................................. 26
6.37 INT P
IN
C
ONTROL
R
EGISTER
( 39H ).......................................................................................................................... 27
6.38 M
ONITOR
R
EGISTER
1 ( 40H )..................................................................................................................................... 27
6.39 M
ONITOR
R
EGISTER
2 ( 41H )..................................................................................................................................... 27
6.40 S
YSTEM
C
LOCK
T
URN
ON C
ONTROL
R
EGISTER
( 50H ) ............................................................................................. 27
6.41 R
ESUME
S
YSTEM
C
LOCK
C
ONTROL
R
EGISTER
( 51H ) ............................................................................................... 27
6.42 M
EMORY
D
ATA
P
RE
-F
ETCH
R
EAD
C
OMMAND WITHOUT
A
DDRESS
I
NCREMENT
R
EGISTER
(F0H) ............................. 27
6.43 M
EMORY
D
ATA
R
EAD
C
OMMAND WITHOUT
A
DDRESS
I
NCREMENT
R
EGISTER
(F1H) ................................................ 28
6.44 M
EMORY
D
ATA
R
EAD
C
OMMAND WITH
A
DDRESS
I
NCREMENT
R
EGISTER
(F2H)....................................................... 28
6.45 M
EMORY
D
ATA
R
EAD
_
ADDRESS
R
EGISTER
(F4H~F5H)............................................................................................ 28
6.46 M
EMORY
D
ATA
W
RITE
C
OMMAND WITHOUT
A
DDRESS
I
NCREMENT
R
EGISTER
(F6H) .............................................. 28
Preliminary
Version: DM9010-17--DS-P04
Jan. 18, 2006
3
DM9010
Single Chip Ethernet Controller with General Processor Interface
6.47 M
EMORY DATA WRITE COMMAND WITH ADDRESS INCREMENT
R
EGISTER
(F8H)........................................................ 28
6.48 M
EMORY DATA WRITE
_
ADDRESS
R
EGISTER
(FAH~FBH).......................................................................................... 28
6.49 TX P
ACKET
L
ENGTH
R
EGISTER
(FCH~FDH)............................................................................................................. 28
6.50 I
NTERRUPT
S
TATUS
R
EGISTER
(FEH) ......................................................................................................................... 28
6.51 I
NTERRUPT
M
ASK
R
EGISTER
(FFH)............................................................................................................................ 29
7. EEPROM FORMAT........................................................................................................................................................ 30
8. MII REGISTER DESCRIPTION ................................................................................................................................... 31
8.1 B
ASIC
M
ODE
C
ONTROL
R
EGISTER
(BMCR) - 00 .......................................................................................................... 32
8.2 B
ASIC
M
ODE
S
TATUS
R
EGISTER
(BMSR) - 01.............................................................................................................. 33
8.3 PHY ID I
DENTIFIER
R
EGISTER
#1 (PHYID1) - 02 ........................................................................................................ 35
8.4 PHY ID I
DENTIFIER
R
EGISTER
#2 (PHYID2) - 03 ........................................................................................................ 35
8.5 A
UTO
-
NEGOTIATION
A
DVERTISEMENT
R
EGISTER
(ANAR) - 04 ................................................................................... 35
8.6 A
UTO
-
NEGOTIATION
L
INK
P
ARTNER
A
BILITY
R
EGISTER
(ANLPAR)
–
05................................................................... 36
8.7 A
UTO
-
NEGOTIATION
E
XPANSION
R
EGISTER
(ANER)- 06............................................................................................. 37
8.8 DAVICOM S
PECIFIED
C
ONFIGURATION
R
EGISTER
(DSCR) - 16................................................................................. 38
8.9 DAVICOM S
PECIFIED
C
ONFIGURATION AND
S
TATUS
R
EGISTER
(DSCSR) - 17.......................................................... 39
8.10 10BASE-T C
ONFIGURATION
/S
TATUS
(10BTCSR) - 18.............................................................................................. 40
8.11 P
OWER
D
OWN
C
ONTROL
R
EGISTER
(PWDOR) - 19 ................................................................................................... 41
8.12 (S
PECIFIED CONFIG
) R
EGISTER
– 20 ............................................................................................................................ 42
9. FUNCTIONAL DESCRIPTION..................................................................................................................................... 43
9.1 H
OST
I
NTERFACE
.......................................................................................................................................................... 43
9.2 D
IRECT
M
EMORY
A
CCESS
C
ONTROL
............................................................................................................................ 43
9.3 P
ACKET
T
RANSMISSION
................................................................................................................................................ 43
9.4 P
ACKET
R
ECEPTION
...................................................................................................................................................... 43
9.5 100B
ASE
-TX O
PERATION
............................................................................................................................................. 44
9.5.1 4B5B Encoder ...................................................................................................................................................... 44
9.5.2 Scrambler ............................................................................................................................................................. 44
9.5.3 Parallel to Serial Converter................................................................................................................................. 44
9.5.4 NRZ to NRZI Encoder .......................................................................................................................................... 44
9.5.5 MLT-3 Converter ................................................................................................................................................. 44
9.5.6 MLT-3 Driver....................................................................................................................................................... 44
9.5.7 4B5B Code Group ................................................................................................................................................ 45
Preliminary
Version: DM9010-17--DS-P04
Jan. 18, 2006
4
DM9010
Single Chip Ethernet Controller with General Processor Interface
9.6 100B
ASE
-TX R
ECEIVER
............................................................................................................................................... 46
9.6.1 Signal Detect ........................................................................................................................................................ 46
9.6.2 Adaptive Equalization .......................................................................................................................................... 46
9.6.3 MLT-3 to NRZI Decoder ...................................................................................................................................... 46
9.6.4 Clock Recovery Module ....................................................................................................................................... 46
9.6.5 NRZI to NRZ ........................................................................................................................................................ 46
9.6.6 Serial to Parallel.................................................................................................................................................. 46
9.6.7 Descrambler......................................................................................................................................................... 46
9.6.8 Code Group Alignment ........................................................................................................................................ 47
9.6.9 4B5B Decoder ...................................................................................................................................................... 47
9.7 10B
ASE
-T O
PERATION
.................................................................................................................................................. 47
9.8 C
OLLISION
D
ETECTION
................................................................................................................................................. 47
9.9 C
ARRIER
S
ENSE
............................................................................................................................................................ 47
9.10 A
UTO
-N
EGOTIATION
.................................................................................................................................................. 47
9.11 P
OWER
R
EDUCED
M
ODE
............................................................................................................................................. 48
9.11.1 Power Down Mode............................................................................................................................................. 48
9.11.2 Reduced Transmit Power Mode ......................................................................................................................... 48
10. DC AND AC ELECTRICAL CHARACTERISTICS ................................................................................................. 49
10.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
................................................................................................................................. 49
10.1.1 Operating Conditions......................................................................................................................................... 49
10.2 DC E
LECTRICAL
C
HARACTERISTICS
(VDD = 3.3V) ................................................................................................... 49
10.3 AC E
LECTRICAL
C
HARACTERISTICS
& T
IMING
W
AVEFORMS
..................................................................................... 50
10.3.1 TP Interface........................................................................................................................................................ 50
10.3.2 Oscillator/Crystal Timing .................................................................................................................................. 50
10.3.3 Processor I/O Read Timing................................................................................................................................ 50
10.3.4 Processor I/O Write Timing ............................................................................................................................... 51
10.3.5 External MII Interface Transmit Timing ............................................................................................................ 52
10.3.6 External MII Interface Receive Timing .............................................................................................................. 52
10.3.7 MII Management Interface Timing .................................................................................................................... 53
10.3.8 EEPROM Interface Timing ................................................................................................................................ 53
11. APPLICATION NOTES................................................................................................................................................ 54
11.1 N
ETWORK
I
NTERFACE
S
IGNAL
R
OUTING
.................................................................................................................... 54
Preliminary
Version: DM9010-17--DS-P04
Jan. 18, 2006
5