64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
s
Single power supply operation
— 2.7 to 3.6 volt read, erase, and program operations
s
SecSi (Secured Silicon) Sector region
— 256-byte sector for permanent, secure identification
through an 8-word random Electronic Serial Number
— May be programmed and locked at the factory or by
the customer
— Accessible through a command sequence
s
VersatileI/O control
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the V
IO
pin
s
Manufactured on 0.17 µm process technology
s
Flexible sector architecture
— One hundred twenty-eight 64 Kbyte sectors
s
Compatibility with JEDEC standards
— Pinout and software compatible with single-power
supply Flash standard
s
Package options
— 56-pin TSOP
— 64-ball Fortified BGA
s
Minimum 1 million erase cycle guarantee per sector
s
20-year data retention at 125°C
s
Program and erase performance (V
HH
not applied to
the ACC input pin)
— Byte program time: 5 µs typical
— Word program time: 7 µs typical
— Sector erase time: 0.6 s typical for each 64 Kbyte
sector
SOFTWARE AND HARDWARE FEATURES
s
Hardware features
—
Ready/Busy# output (RY/BY#):
indicates program or
erase cycle completion
—
Hardware reset input (RESET#):
resets device for
new operation
— WP# input protects first or last 64 Kbyte sector
regardless of sector protection settings
—
ACC input:
Accelerates programming time for higher
throughput during system production
s
Software features
—
Program Suspend & Resume:
read other sectors
before programming operation is completed
—
Sector Group Protection:
V
CC
-level method of
preventing program or erase operations within a
sector
—
Temporary Sector Group Unprotect:
V
ID
-level method
of changing in previously locked sectors
—
CFI (Common Flash Interface) compliant:
allows host
system to identify and accommodate multiple flash
devices
—
Erase Suspend/Erase Resume:
read/program other
sectors before an erase operation is complete
—
Data# Polling
and
toggle bits
provide erase and
programming operation status
—
Unlock Bypass Program
command reduces overall
multiple-word programming time
PERFORMANCE CHARCTERISTICS
s
High performance
— Access time ratings as fast as 55 ns
s
Ultra low power consumption (typical values at 3.0 V,
5 MHz)
— 9 mA typical active read current
— 26 mA typical erase/program current
— 200 nA typical standby mode current
his Data Sheet states AMD’s current technological specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or
odifications due to changes in technical specifications. This document contains information on a product under development at Advanced Micro Devices. The
nformation is intended to help you evaluate this product. Do not design in this product without contacting the factory. AMSD reserves the right to change or discontinue
ork on this proposed product without notice.
Publication#
25293
Rev:
A
Amendment/+2
Issue Date:
October 18, 2002
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV640GH/L is a 64 Mbit, 3.0 volt (2.7 V to
3.6 V) single power supply flash memory devices or-
ganized as 4,194,304 words or 8,388,608 bytes. Data
a p pe a r s o n D Q1 5 –D Q0 i n w or d m o d e a n d o n
DQ7–DQ0 in byte mode. The device is designed to be
programmed in-system with the standard system 3.0
volt V
CC
supply. A 12.0 volt V
PP
is not required for pro-
gram or erase operations. The device can also be pro-
grammed in standard EPROM programmers.
Access times of 55 regulated voltage and 70 ns full
voltage range are available for applications where V
IO
≥
V
CC
. The device is offered in 56-pin TSOP and
64-ball Fortified BGA packages. To eliminate bus con-
tention each device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
Each device requires only a
single 3.0 volt power
supply
(2.7 V to 3.6 V) for both read and write func-
tions. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation. Dur-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The
VersatileI/O™
(V
IO
) control allows the host sys-
tem to set the voltage levels that the device generates
at its data outputs and the voltages tolerated at its
data inputs to the same voltage level that is asserted
on the V
IO
pin. This allows the device to operate in 1.8
V or 3 V system environment as required.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6 (tog-
gle)
status bits.
After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
3
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved. The
Program Suspend/Program
Resume
feature enables the host system to pause a
program operation in a given sector to read any other
sector and then complete the program operation.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read boot-up firmware from the Flash mem-
ory device.
The device offers a
standby mode
as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
The
SecSi (Secured Silicon) Sector
provides an
minimum 128-word area for code or data that can be
permanently protected. Once this sector is protected,
no further programming or erasing within the sector
can occur.
The
Write Protect (WP#)
feature protects the first or
last sector by asserting a logic low on the WP# pin.
The protected sector will still be protected even during
accelerated programming.
The
accelerated program (ACC)
feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to V
HH
, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increase factory throughput during sys-
tem production, but may also be used in the field if de-
sired.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
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