MC74VHC1GT50DFR2 datasheet, PDF

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MC74VHC1GT50DFR2: DescriptionAHC/VHC SERIES, 1-INPUT NON-INVERT GATE, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN; Categorylogic logic; File Size120KB，6 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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MC74VHC1GT50DFR2 Overview

AHC/VHC SERIES, 1-INPUT NON-INVERT GATE, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN

MC74VHC1GT50DFR2 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	ON Semiconductor
Parts packaging code	SOT-353
package instruction	TSSOP,
Contacts	5
Reach Compliance Code	compliant
series	AHC/VHC
JESD-30 code	R-PDSO-G5
JESD-609 code	e0
length	2 mm
Logic integrated circuit type	BUFFER
Number of functions	1
Number of entries	1
Number of terminals	5
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240
propagation delay (tpd)	9.5 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	1.25 mm

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MC74VHC1GT50

Noninverting Buffer /

CMOS Logic Level Shifter

TTL−Compatible Inputs

The MC74VHC1GT50 is a single gate noninverting buffer

fabricated with silicon gate CMOS technology. It achieves high speed

operation similar to equivalent Bipolar Schottky TTL while

maintaining CMOS low power dissipation.

The internal circuit is composed of three stages, including a buffer

output which provides high noise immunity and stable output.

The device input is compatible with TTL−type input thresholds and

the output has a full 5 V CMOS level output swing. The input protection

circuitry on this device allows overvoltage tolerance on the input,

allowing the device to be used as a logic−level translator from 3 V

CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V

CMOS Logic while operating at the high−voltage power supply.

The MC74VHC1GT50 input structure provides protection when

voltages up to 7 V are applied, regardless of the supply voltage. This

allows the MC74VHC1GT50 to be used to interface high voltage to

low voltage circuits. The output structures also provide protection

when V

= 0 V. These input and output structures help prevent

device destruction caused by supply voltage

−

input/output voltage

mismatch, battery backup, hot insertion, etc.

Features

http://onsemi.com

MARKING

DIAGRAMS

SC−88A / SOT−353 / SC−70

DF SUFFIX

CASE 419A

VL M

TSOP−5 / SOT−23 / SC−59

DT SUFFIX

CASE 483

VL M

•

Designed for 1.65 V to 5.5 V

Operation

High Speed: t

= 3.5 ns (Typ) at V

= 5 V

Low Power Dissipation: I

= 1

(Max) at T

= 25°C

TTL−Compatible Inputs: V

= 0.8 V; V

= 2.0 V, V

= 5 V

CMOS−Compatible Outputs: V

> 0.8 V

; V

< 0.1 V

@Load

Power Down Protection Provided on Inputs and Outputs

Balanced Propagation Delays

Pin and Function Compatible with Other Standard Logic Families

= Device Code

= Date Code*

= Pb−Free Package

(Note: Microdot may be in either location)

*Date Code orientation and/or position may vary

depending upon manufacturing location.

Chip Complexity: FETs = 104; Equivalent Gates = 26

NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

•

These Devices are Pb−Free and are RoHS Compliant

OUT Y

PIN ASSIGNMENT

IN A

GND

OUT Y

IN A

GND

FUNCTION TABLE

A Input

Y Output

Figure 1. Pinout

(Top View)

IN A

OUT Y

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

Figure 2. Logic Symbol

Semiconductor Components Industries, LLC, 2013

February, 2013

−

Rev. 15

Publication Order Number:

MC74VHC1GT50/D

MC74VHC1GT50DFR2 Related Products

	MC74VHC1GT50DFR2	MC74VHC1GT50DFT1G	MC74VHC1GT50DFT2G	MC74VHC1GT50DFT4	MC74VHC1GT50DTT3
Description	AHC/VHC SERIES, 1-INPUT NON-INVERT GATE, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN	AHC/VHC SERIES, 1-INPUT NON-INVERT GATE, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN	AHC/VHC SERIES, 1-INPUT NON-INVERT GATE, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN	AHC/VHC SERIES, 1-INPUT NON-INVERT GATE, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN	AHC/VHC SERIES, 1-INPUT NON-INVERT GATE, PDSO5, SC-59, SOT-23, TSOP-5
Is it Rohs certified?	incompatible	conform to	conform to	incompatible	incompatible
Maker	ON Semiconductor	ON Semiconductor	ON Semiconductor	ON Semiconductor	ON Semiconductor
Parts packaging code	SOT-353	SOT-353	SOT-353	SOT-353	TSOP
package instruction	TSSOP,	TSSOP,	SC-70, SC-88A, SOT-353, 5 PIN	TSSOP, TSSOP5/6,.08	TSOP, TSOP5/6,.11,37
Contacts	5	5	5	5	5
Reach Compliance Code	compliant	compliant	compliant	not_compliant	not_compliant
series	AHC/VHC	AHC/VHC	AHC/VHC	AHC/VHC	AHC/VHC
JESD-30 code	R-PDSO-G5	R-PDSO-G5	R-PDSO-G5	R-PDSO-G5	R-PDSO-G5
length	2 mm	2 mm	2 mm	2 mm	3 mm
Logic integrated circuit type	BUFFER	BUFFER	BUFFER	BUFFER	BUFFER
Number of functions	1	1	1	1	1
Number of entries	1	1	1	1	1
Number of terminals	5	5	5	5	5
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP	TSSOP	TSSOP	TSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	240	265	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
propagation delay (tpd)	9.5 ns	25.5 ns	25.5 ns	17.5 ns	17.5 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	1.1 mm	1.1 mm	1.1 mm	1.1 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	1.65 V	1.65 V	3 V	3 V
Nominal supply voltage (Vsup)	5 V	1.8 V	1.8 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.95 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	40	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	1.25 mm	1.25 mm	1.25 mm	1.25 mm	1.5 mm
JESD-609 code	e0	e3	-	e0	e0
Terminal surface	TIN LEAD	MATTE TIN	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)

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