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Data Sheet
FEATURES
250 kSPS, 6-Channel, Simultaneous
Sampling, Bipolar, 16-/14-/12-Bit ADC
AD7656-1/AD7657-1/AD7658-1
FUNCTIONAL BLOCK DIAGRAM
V
DD
CONVST A CONVST B CONVST C AV
CC
DV
CC
CS
SER/PAR SEL
V
DRIVE
STBY
BUF
V1
T/H
16-/14-/
12-BIT SAR
OUTPUT
DRIVERS
DB8/DOUT A
Pin and software compatible with AD7656/AD7657/AD7658
featuring reduced decoupling requirements
6 independent ADCs
True bipolar analog inputs
Pin-/software-selectable ranges: ±10 V, ±5 V
Fast throughput rate: 250 kSPS
iCMOS
process technology
Low power
140 mW at 250 kSPS with 5 V supplies
High noise performance with wide bandwidth
88 dB SNR at 10 kHz input frequency
On-chip reference and reference buffers
High speed parallel, serial, and daisy-chain interface modes
High speed serial interface
SPI/QSPI™/MICROWIRE™/DSP compatible
Standby mode: 315 µW maximum
64-lead LQFP
REF
CLK
OSC
CONTROL
LOGIC
DB6/SCLK
V2
T/H
BUF
V3
T/H
16-/14-/
12-BIT SAR
16-/14-/
12-BIT SAR
OUTPUT
DRIVERS
OUTPUT
DRIVERS
DB9/DOUT B
DB10/DOUT C
V4
T/H
BUF
16-/14-/
12-BIT SAR
OUTPUT
DRIVERS
DATA/
CONTROL
LINES
RD
WR/REF
EN/DIS
V5
T/H
16-/14-/
12-BIT SAR
Power line monitoring and measuring systems
Instrumentation and control systems
Multiaxis positioning systems
AD7656-1/AD7657-1/AD7658-1
V
SS
AGND
DGND
Figure 1.
GENERAL DESCRIPTION
The AD7656-1/AD7657-1/AD7658-1
1
are reduced decoupling pin-
and software-compatible versions of
AD7656/AD7657/AD7658.
The AD7656-1/AD7657-1/AD7658-1 devices contain six 16-/
14-/12-bit, fast, low power successive approximation ADCs in
a package designed on the
iCMOS®
process (industrial CMOS).
iCMOS
is a process combining high voltage silicon with submicron
CMOS and complementary bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no previous generation
of high voltage parts could achieve. Unlike analog ICs using conven-
tional CMOS processes,
iCMOS
components can accept bipolar
input signals while providing increased performance, which
dramatically reduces power consumption and package size.
The AD7656-1/AD7657-1/AD7658-1 feature throughput rates
of up to 250 kSPS. The parts contain low noise, wide bandwidth
track-and-hold amplifiers that can handle input frequencies
up to 4.5 MHz.
The conversion process and data acquisition are controlled
using the CONVST signals and an internal oscillator. Three
CONVST pins (CONVST A, CONVST B, and CONVST C)
allow independent, simultaneous sampling of the three ADC
pairs. The AD7656-1/AD7657-1/AD7658-1 have a high speed
parallel and serial interface, allowing the devices to interface with
microprocessors or DSPs. When the serial interface is selected,
each part has a daisy-chain feature that allows multiple ADCs to
connect to a single serial interface. The AD7656-1/AD7657-1/
AD7658-1 can accommodate true bipolar input signals in the
±4 × V
REF
and ±2 × V
REF
ranges. Each AD7656-1/AD7657-1/
AD7658-1 also contains an on-chip 2.5 V reference.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
Six 16-/14-/12-bit, 250 kSPS ADCs on board.
Six true bipolar, high impedance analog inputs.
High speed parallel and serial interfaces.
Reduced decoupling requirements and reduced bill of
materials cost compared with the AD7656/AD7657/
AD7658 devices.
1
Protected by U.S. Patent No. 6,731,232.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.
07017-001
APPLICATIONS
V6
T/H
16-/14-/
12-BIT SAR
AD7656-1/AD7657-1/AD7658-1
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD7656-1 ...................................................................................... 3
AD7657-1 ...................................................................................... 5
AD7658-1 ...................................................................................... 7
Timing Specifications .................................................................. 9
Absolute Maximum Ratings .......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 14
Terminology .................................................................................... 18
Data Sheet
Theory of Operation ...................................................................... 20
Converter Details ....................................................................... 20
ADC Transfer Function ............................................................. 21
Internal/External Reference ...................................................... 21
Typical Connection Diagram ................................................... 21
Driving the Analog Inputs ........................................................ 22
Interface Options ........................................................................ 22
Software Selection of ADCs ...................................................... 24
Changing the Analog Input Range (H/S SEL = 0) ................ 25
Changing the Analog Input Range (H/S SEL = 1) ................ 25
Serial Read Operation................................................................ 25
Daisy-Chain Mode (DCEN = 1, SER/PAR SEL = 1) ............. 27
Application Hints ........................................................................... 29
Layout .......................................................................................... 29
Power Supply Configuration..................................................... 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
REVISION HISTORY
3/12—Rev. C to Rev. D
Changes to Figure 28 ...................................................................... 22
11/10—Rev. B to Rev. C
Added Power Supply Configuration Section .............................. 29
Added Figure 39.............................................................................. 29
6/10—Rev. A to Rev. B
Changes to DC Accuracy Parameter, Table 1 ............................... 3
Changes to DC Accuracy Parameter, Table 2 ............................... 5
Change to DC Accuracy Parameter, Table 3 ................................. 7
Added %FSR to Terminology Section ......................................... 19
3/09—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Table 3.............................................................................7
Changes to Table 4.............................................................................9
Changes to Absolute Maximum Ratings Table .......................... 10
Changes to Pin Functions Description Table ............................. 11
Changes to Figure 9 ........................................................................ 14
Changes to Converter Details Section ......................................... 20
Changes to Internal/External Reference Section ....................... 21
Changes to Interface Options Section ......................................... 22
Changes to Parallel Interface Section .......................................... 22
Changes to Serial Interface (SER/PAR SEL = 1) Section .......... 25
Changes to Daisy-Chain Mode (DCEN = 1, SER/PAR SEL = 1) .. 27
Changes to Layout Section ............................................................ 30
Updated Outline Dimension ........................................................ 31
Changes to Ordering Guide .......................................................... 31
7/08—Revision 0: Initial Version
Rev. D | Page 2 of 32
Data Sheet
SPECIFICATIONS
AD7656-1
AD7656-1/AD7657-1/AD7658-1
V
REF
= 2.5 V internal/external, AV
CC
= 4.75 V to 5.25 V, DV
CC
= 4.75 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25 V; for the ±4 × V
REF
range, V
DD
=
10 V to 16.5 V, V
SS
= −10 V to −16.5 V; for the ±2 × V
REF
range, V
DD
= 5 V to 16.5 V, V
SS
= −5 V to −16.5 V; f
SAMPLE
= 250 kSPS, T
A
= T
MIN
to
T
MAX
, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)
1
Signal-to-Noise Ratio (SNR)
1
Total Harmonic Distortion (THD)
1
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
1
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Delay Matching
Aperture Jitter
Channel-to-Channel Isolation
1
Full-Power Bandwidth
DC ACCURACY
Resolution
No Missing Codes
B Version
Y Version
Integral Nonlinearity
1
Positive Full-Scale Error
Positive Full-Scale Error Matching
1
Bipolar Zero-Scale Error
1
B Version
Y Version
Bipolar Zero-Scale Error Matching
1
Negative Full-Scale Error
1
Negative Full-Scale Error Matching
1
ANALOG INPUT
Input Voltage Ranges
1
1
Min
Typ
88
88
Max
Unit
dB
dB
dB
dB
dB
dB
dB
ns
ns
ps
dB
MHz
MHz
Bits
Bits
Bits
LSB
LSB
% FSR
% FSR
% FSR
%F SR
% FSR
% FSR
% FSR
V
V
µA
pF
pF
V
µA
pF
V
ppm
ppm/°C
ppm/°C
Test Conditions/Comments
f
IN
= 10 kHz sine wave
−90
−105
−100
−112
−107
10
4
35
−100
4.5
2.2
16
15
14
±3
±1
±0.8
±0.35
±0.048
±0.048
±0.038
±0.8
±0.35
−4 × V
REF
−2 × V
REF
10
14
2.5
18.5
2.49
150
25
6
Rev. D | Page 3 of 32
V
DD
/V
SS
= ±5 V to ±16.5 V
fa = 10.5 kHz, fb = 9.5 kHz
f
IN
on unselected channels up to 100 kHz
@ −3 dB
@ −0.1 dB
±0.381% FSR typical
±0.0137% FSR typical
±0.381% FSR typical
See Table 8 for minimum V
DD
/V
SS
for each range
RNGx bits or RANGE pin = 0
RNGx bits or RANGE pin = 1
±4 × V
REF
range when in track
±2 × V
REF
range when in track
DC Leakage Current
Input Capacitance
2
REFERENCE INPUT/OUTPUT
Reference Input Voltage Range
DC Leakage Current
Input Capacitance
2
Reference Output Voltage
Long-Term Stability
Reference Temperature Coefficient
+4 × V
REF
+2 × V
REF
±1
2.5
±1
2.51
REF
EN/DIS
= 1
1000 hours
AD7656-1/AD7657-1/AD7658-1
Parameter
LOGIC INPUTS
Input High Voltage (V
INH
)
Input Low Voltage (V
INL
)
Input Current (I
IN
)
Input Capacitance (C
IN
)
2
LOGIC OUTPUTS
Output High Voltage (V
OH
)
Output Low Voltage (V
OL
)
Floating-State Leakage Current
Floating-State Output Capacitance
2
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
1, 2
Throughput Rate
POWER REQUIREMENTS
V
DD
V
SS
AV
CC
DV
CC
V
DRIVE
I
TOTAL 3
Normal Mode—Static
Normal Mode—Operational
I
SS
(Operational)
I
DD
(Operational)
Partial Power-Down Mode
Full Power-Down Mode (STBY Pin)
Power Dissipation
Normal Mode—Static
Normal Mode—Operational
Partial Power-Down Mode
Full Power-Down Mode (STBY Pin)
See the Terminology section.
Sample tested during initial release to ensure compliance.
3
Includes I
AVCC
, I
VDD
, I
VSS
, I
VDRIVE
, and I
DVCC
.
1
2
Data Sheet
Typ
Max
Unit
V
V
µA
pF
V
V
µA
pF
Test Conditions/Comments
Min
0.7 × V
DRIVE
0.3 × V
DRIVE
±10
10
V
DRIVE
− 0.2
0.2
±10
10
Twos
complement
3.1
550
250
−5
−5
4.75
4.75
2.7
+16.5
−16.5
5.25
5.25
5.25
18
26
0.25
0.25
7
60
Typically 10 nA, V
IN
= 0 V or V
DRIVE
I
SOURCE
= 200 µA
I
SINK
= 200 µA
µs
ns
kSPS
V
V
V
V
V
mA
mA
mA
mA
mA
µA
Parallel interface mode only
For the 4 × V
REF
range, V
DD
= 10 V to 16.5 V
For the 4 × V
REF
range, V
SS
= −10 V to −16.5 V
Digital inputs = 0 V or V
DRIVE
AV
CC
= DV
CC
= V
DRIVE
= +5.25 V, V
DD
= +16.5 V,
V
SS
= −16.5 V
f
SAMPLE
= 250 kSPS, AV
CC
= DV
CC
= V
DRIVE
= +5.25 V,
V
DD
= +16.5 V, V
SS
= −16.5 V
V
SS
= −16.5 V, f
SAMPLE
= 250 kSPS
V
DD
= +16.5 V, f
SAMPLE
= 250 kSPS
AV
CC
= DV
CC
= V
DRIVE
= +5.25 V, V
DD
= +16.5 V,
V
SS
= −16.5 V
SCLK on or off, AV
CC
= DV
CC
= V
DRIVE
= +5.25 V,
V
DD
= +16.5 V, V
SS
= −16.5 V
AV
CC
= DV
CC
= V
DRIVE
= +5.25 V, V
DD
= +16.5 V,
V
SS
= −16.5 V
f
SAMPLE
= 250 kSPS
94
140
40
315
mW
mW
mW
µW
Rev. D | Page 4 of 32
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