Latch-up Current...................................................... >200 mA
Operating Range
Device
CY62157DVL
CY62157DVLL
Range
Industrial
Ambient
Temperature (T
A
)
–40°C to +85°C
V
CC
[5]
2.20V to
3.60V
Product Portfolio
Power Dissipation
Product
Min.
CY62157DVL
CY62157DVLL
2.20
2.20
V
CC
Range (V)
Typ.
[6]
3.0
3.0
Max.
3.60
3.60
55
55
Speed
(ns)
Operating I
CC
, (mA)
f = 1MHz
Typ.
[6]
1.5
1.5
Max.
3
3
f = f
max
Typ.
[6]
12
12
Max.
20
15
Standby I
SB2
, (µA)
Typ.
[6]
2
2
Max.
20
8
Electrical Characteristics
Over the Operating Range
CY62157DV-55
Parameter
V
OH
V
OL
V
IH[7]
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply
Current
I
OH
= –0.1 mA
I
OH
= –1.0 mA
I
OL
= 0.1 mA
I
OL
= 2.1mA
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
f = f
MAX
= 1/t
RC
f = 1 MHz
I
SB1
Automatic CE
Power-Down
Current — CMOS
Inputs
Automatic CE
Power-Down
Current — CMOS
Inputs
CE
1
> V
CC
−0.2V,
CE
2
< 0.2V
V
IN
>V
CC
–0.2V, V
IN
<0.2V)
f = f
MAX
(Address and Data Only),
f = 0 (OE, WE, BHE and BLE), V
CC
=3.60V
CE
1
> V
CC
– 0.2V or CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= 3.60V
V
CC
= V
CCmax
L
I
OUT
= 0 mA
LL
CMOS levels
L
LL
L
LL
L
LL
2
2
2
2
Test Conditions
V
CC
= 2.20V
V
CC
= 2.70V
V
CC
= 2.20V
V
CC
= 2.70V
1.8
2.2
–0.3
–0.3
–1
–1
12
Min. Typ.
[6]
2.0
2.4
0.4
0.4
V
CC
+ 0.3V
V
CC
+ 0.3V
0.6
0.8
+1
+1
20
15
1.5
3
3
20
8
20
8
µA
Max.
Unit
V
V
V
V
V
V
V
V
µA
µA
mA
mA
mA
mA
µA
I
SB2
Notes:
4. V
IL(min.)
= –2.0V for pulse durations less than 20 ns.
5. Full Device AC operation requires linear Vcc ramp from 0 to Vcc(min) >= 500
µs.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25°C.
7. V
IH(max)
= V
CC
+0.75V for pulse duration less than 20 ns.
Document #: 38-05392 Rev. *B
Page 3 of 12
CY62157DV
PRELIMINARY
Capacitance
[8]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max.
6
8
Unit
pF
pF
MoBL
®
Thermal Resistance
[8]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
BGA
55
16
TSOP II
TBD
TBD
TSOP I
TBD
TBD
Unit
°C/W
°C/W
AC Test Loads and Waveforms
V
CC
OUTPUT
R1
V
CC
GND
10%
R2
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
50 pF
INCLUDING
JIG AND
SCOPE
Rise Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
R
TH
OUTPUT
V
Parameters
R1
R2
R
TH
V
TH
2.50V
16667
15385
8000
1.20
3.0V
1103
1554
645
1.75
Unit
Ω
Ω
Ω
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.5V
CE
1
> V
CC
– 0.2V, CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
L
LL
0
t
RC
Conditions
Min.
1.5
Typ.
[6]
Max.
2.2
10
4
ns
ns
Unit
V
µA
t
CDR[8]
Chip Deselect to Data Retention Time
t
R[9]
Operation Recovery Time
Notes:
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100 us or stable at V
CC(min.)
> 100 us.
Document #: 38-05392 Rev. *B
Page 4 of 12
CY62157DV
PRELIMINARY
Data Retention Waveform
[10]
V
CC
CE
1 or
BHE
.
BLE
MoBL
®
V
CC
, min.
t
CDR
DATA RETENTION MODE
V
DR
> 1.5 V
V
CC
, min.
t
R
or
CE2
Switching Characteristics
Over the Operating Range
[11]
55 ns
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Cycle
[14]
Write Cycle Time
CE
1
LOW and CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE / BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[12, 13]
WE HIGH to Low-Z
[12]
10
55
40
40
0
0
40
40
25
0
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z
[12]
OE HIGH to High
Z
[12, 13]
Z
[12]
Z
[12, 13]
0
55
55
10
20
10
20
CE
1
LOW and CE
2
HIGH to Low
CE
1
HIGH and CE
2
LOW to High
5
20
10
55
25
55
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Unit
CE
1
LOW and CE
2
HIGH to Power-Up
CE
1
HIGH and CE
2
LOW to Power-Down
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z
[12]
BLE / BHE HIGH to HIGH
Z
[12, 13]
Notes:
10. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
11. Test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
CC(typ.)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
12. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
13. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedence state.Transition is measured +/-200mV from steady state voltage.
14. The internal Write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE = V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
[i=s]This post was last edited by nemo1991 on 2016-3-5 20:39[/i] [align=left][align=left]Time flies. I saw the event on forum F7 at the beginning of the semester and decided to participate. It took me...
[align=left][size=5][color=#0000ff]The national competition is about to begin! If you are still unclear about the specific arrangements for the national competition, please check it out [/color][/size...
I am using Cyclone V FPGA to receive 8-channel differential data, 12bit, 600M data rate. The data received by LVDS_RX core is incorrect. The 8-channel data is not synchronized. Can anyone tell me how ...
The TIA Portal software's shift instructions shift the contents of an accumulator bit by bit to the left or right. The number of bits shifted is determined by N. A left shift of N bits multiplies t...[Details]
On August 24th, Jin Yuzhi, CEO of Huawei's Intelligent Automotive Solutions BU, announced the first automotive application of Huawei Qiankun's unique Limera technology. This technology eliminates t...[Details]
On August 25th, Apple's expansion in India encountered new troubles. According to Bloomberg, Foxconn Technology Group has recalled approximately 300 Chinese engineers from India, further hindering ...[Details]
The difference between a series inverter and a parallel inverter is that they use different oscillation circuits. A series inverter connects L, R, and C in series, while a parallel inverter connect...[Details]
Batteries, at the core of new energy vehicles, are crucial to vehicle performance and range. Existing automotive batteries are categorized into lead-acid and lithium batteries. Currently, new energ...[Details]
Wearable technology is taking off, with applications evolving rapidly, from smartwatches to fitness trackers and even smart wigs! Bluetooth Smart is at the center of this revolution. This is the se...[Details]
introduction
The rapid development of science and technology has enabled mankind to quickly move from the Internet era to the big data era. As a result, the amount of data generated by people ...[Details]
A new multi-layer diffractive optical processor can block images in one direction while allowing images in another direction to pass through.
Researchers at the University of California,...[Details]
With the development of vehicle technology, there are more types of cars. Cars are divided into hybrid, pure electric vehicles, and fuel vehicles. For hybrid cars, they are divided into plug-in hyb...[Details]
While aberration theory is a vast subject, a basic understanding of some fundamental concepts can make it easier to understand: spherical aberration, astigmatism, field curvature, and chromatic abe...[Details]
For traditional gasoline vehicles, the engine and transmission are the core components of the entire vehicle, while for pure electric vehicles, the power battery is clearly the most important. Ther...[Details]
The number of new energy vehicles in use is increasing, and there are multiple choices available. New energy vehicles can be divided into hybrid and pure electric, and the types of hybrid include m...[Details]
1. Introduction to power amplifier circuit
1. Generally speaking, the main function of a power amplifier circuit is to allow the load to obtain maximum power without distorting the signal or c...[Details]
We often notice that some safety light curtains have EDM function. What does EDM mean here? What is its function?
The full name of EDM is External Device Monitor, which means external device m...[Details]
On August 8, PetroChina Southwest Oil & Gas Field Company's 35kV Zhouping Line centralized battery energy storage system successfully completed a 24/7 trial run, achieving full compliance with all ...[Details]
stm32/stm8
京公网安备 11010802033920号
EEWORLD
