USE ULTRA37000™
FOR ALL NEW DESIGNS
CY7C372i
UltraLogic™ 64-Macrocell Flash CPLD
Features
• 64 macrocells in four logic blocks
• 32 I/O pins
• Five dedicated inputs including two clock pins
• In-System Reprogrammable (ISR™) Flash technology
— JTAG interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
— f
MAX
= 125 MHz
— t
PD
= 10 ns
— t
S
= 5.5 ns
— t
CO
= 6.5 ns
• Fully PCI compliant
• 3.3V or 5.0V I/O operation
• Available in 44-pin PLCC, TQFP, and CLCC packages
• Pin-compatible with the CY7C371i
Functional Description
The CY7C372i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370i™ family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C372i is
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic™ F
LASH
370i devices, the CY7C372i
is electrically erasable and ISR, which simplifies both design
and manufacturing flows, thereby reducing costs. The
Cypress ISR function is implemented through a JTAG serial
interface. Data is shifted in and out through the SDI and SDO
pins. The ISR interface is enabled using the programming
voltage pin (ISR
EN
). Additionally, because of the superior
routability of the F
LASH
370i devices, ISR often allows users to
change existing logic designs while simultaneously fixing
pinout assignments.
The 64 macrocells in the CY7C372i are divided between four
logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
The logic blocks in the F
LASH
370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Logic Block Diagram
INPUTS
CLOCK
INPUTS
2
INPUT/CLOCK
MACROCELLS
2
LOGIC
BLOCK
D
8 I/Os
I/O
24
-I/O
31
3
INPUT
MACROCELLS
2
8 I/Os
I/O
0
-I/O
7
LOGIC
BLOCK
A
36
16
PIM
36
16
8 I/Os
I/O
8
-I/O
15
LOGIC
BLOCK
B
36
16
36
16
LOGIC
BLOCK
C
8 I/Os
I/O
16
-I/O
23
16
16
Cypress Semiconductor Corporation
Document #: 38-03033 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised April 16, 2004
USE ULTRA37000™
FOR ALL NEW DESIGNS
Functional Description
Like all members of the F
LASH
370i family, the CY7C372i is rich
in I/O resources. Every two macrocells in the device feature
an associated I/O pin, resulting in 32 I/O pins on the
CY7C372i. In addition, there are three dedicated inputs and
two input/clock pins.
Finally, the CY7C372i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect
delays, or expander delays. Regardless of the number of
resources used. or the type of application, the timing param-
eters on the CY7C372i remain the same.
Logic Block
The number of logic blocks distinguishes the members of the
F
LASH
370i family. The CY7C372i includes four logic blocks.
Each logic block is constructed of a product term array, a
product term allocator, and 16 macrocells.
Product Term Array
The product term array in the F
LASH
370i logic block includes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are
available in both positive and negative polarity, making the
overall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in a
single pass through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the F
LASH
370 PLDs. Note that product term allocation is
handled by software and is invisible to the user.
I/O Macrocell
Half of the macrocells on the CY7C372i have separate I/O pins
associated with them. In other words, each I/O pin is shared
by two macrocells. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term
allocator. The macrocell includes a register that can be
optionally bypassed. It also has polarity control, and two global
clocks to trigger the register. The I/O macrocell also features
a separate feedback path to the PIM so that the register can
be buried if the I/O pin is used as an input.
Buried Macrocell
The buried macrocell is very similar to the I/O macrocell.
Again, it includes a register that can be configured as combi-
natorial, as a D flip-flop, a T flip-flop, or a latch. The clock for
this register has the same options as described for the I/O
macrocell. One difference on the buried macrocell is the
addition of input register capability. The user can program the
buried macrocell to act as an input register (D-type or latch)
whose input comes from the I/O pin associated with the neigh-
CY7C372i
boring macrocell. The output of all buried macrocells is sent
directly to the PIM regardless of its configuration.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
four logic blocks on the CY7C372i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the F
LASH
370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An
Introduction to In System Reprogramming with F
LASH
370i.”
PCI Compliance
The F
LASH
370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
F
LASH
370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term distri-
bution.
3.3V or 5.0V I/O operation
The F
LASH
370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of V
CC
pins:
one set, V
CCINT
, for internal operation and input buffers, and
another set, V
CCIO
, for I/O output drivers. V
CCINT
pins must
always be connected to a 5.0V power supply. However, the
V
CCIO
pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When V
CCIO
pins are connected to a 5.0V source, the I/O voltage levels are
compatible with 5.0V systems. When V
CCIO
pins are
connected to a 3.3V source, the input voltage levels are
compatible with both 5.0V and 3.3V systems, while the output
voltage levels are compatible with 3.3V systems. There will be
an additional timing delay on all output buffers when operating
in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is
available in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold has
been added to all F
LASH
370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus
reducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to V
CC
or GND.
Design Tools
Development software for the CY7C372i is available from
Cypress’s
Warp™, Warp
Professional™, and
Warp
Enter-
prise™ software packages. Please refer to the data sheets on
these products for more details. Cypress also actively
supports almost all third-party design tools. Please refer to
third-party tool support for further information.
Page 3 of 13
Document #: 38-03033 Rev. *A
USE ULTRA37000™
FOR ALL NEW DESIGNS
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
DC Program Voltage .....................................................12.5V
CY7C372i
Output Current into Outputs ........................................ 16 mA
Static Discharge Voltage........................................... > 2001V
(per MIL–STD–883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Military
[2]
Ambient
Temperature
0°C to +70°C
−40°C
to +85°C
–55°C to +125°C
V
CC
V
CCINT
V
CCIO
5V
±
0.25V 5V
±
0.25V or
3.3V
±
0.3V
5V
±
0.5V
5V
±
0.5V
5V
±
0.5V
3.3V
±
0.3V
Electrical Characteristics
Over the Operating Range
[3, 4]
Parameter
V
OH
V
OHZ
V
OL
V
IH
V
IL
I
IX
I
OZ
Description
Output HIGH Voltage
Output HIGH Voltage with
Output Disabled
[8]
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Test Conditions
V
CC
= Min. I
OH
= –3.2 mA (Com’l/Ind)
I
OH
= –2.0 mA (Mil)
V
CC
= Max. I
OH
= 0
µA
(Com’l/Ind)
[5, 6]
I
OH
= –50
µA
(Com’l/Ind)
[5, 6]
V
CC
= Min. I
OL
= 16 mA (Com’l/Ind)
[5]
I
OL
= 12 mA (Mil)
Guaranteed Input Logical HIGH Voltage for all
Inputs
[7]
Guaranteed Input Logical LOW Voltage for all
Inputs
[7]
V
I
= Internal GND, V
I
= V
CC
V
CC
= Max., V
O
= GND or V
O
= V
CC
, Output
Disabled
V
CC
= Max., V
O
= 3.3V, Output Disabled
[6]
I
OS
I
CC
Output Short
Circuit Current
[8, 9]
Power Supply Current
[10]
V
CC
= Max., V
OUT
= 0.5V
V
CC
= Max., I
OUT
= 0 mA,
f = 1 MHz, V
IN
= GND, V
CC
V
CC
= Min., V
IL
= 0.8V
V
CC
= Min., V
IH
= 2.0V
V
CC
= Max.
V
CC
= Max.
Com’l/Ind.
Com’l “L” –66
Military
I
BHL
I
BHH
I
BHLO
I
BHHO
Input Bus Hold LOW
Sustaining Current
Input Bus Hold HIGH
Sustaining Current
Input Bus Hold LOW
Overdrive Current
Input Bus Hold HIGH
Overdrive Current
+75
–75
+500
−500
2.0
–0.5
–10
–50
0
–30
75
45
75
–70
[5]
Min.
2.4
2.4
Typ.
Max.
Unit
V
V
4.0
3.6
0.5
0.5
7.0
0.8
+10
+50
–125
–160
125
75
200
V
V
V
V
V
V
µA
µA
µA
mA
mA
mA
mA
µA
µA
µA
µA
Notes:
2. T
A
is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. If V
CCIO
is not specified, the device can be operating in either 3.3V or 5V I/O mode; V
CC
= V
CCINT
.
5. For SDO: I
OH
=–2 mA, I
OL
= 2 mA.
6. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly
by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note “Understanding Bus Hold” for additional
information.
7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V
OUT
= 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
9. Tested initially and after any design or process changes that may affect these parameters.
10. Measured with 16-bit counter programmed into each logic block.
Document #: 38-03033 Rev. *A
Page 4 of 13
京公网安备 11010802033920号
EEWORLD
