Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDIP14, 0.300 INCH, DIP-14
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | DALLAS |
| package instruction | 0.300 INCH, DIP-14 |
| Reach Compliance Code | unknown |
| series | 1000 |
| JESD-30 code | R-PDIP-T14 |
| JESD-609 code | e0 |
| Logic integrated circuit type | SILICON DELAY LINE |
| Number of functions | 1 |
| Number of taps/steps | 5 |
| Number of terminals | 14 |
| Maximum operating temperature | 85 °C |
| Minimum operating temperature | -40 °C |
| Output polarity | TRUE |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | DIP |
| Encapsulate equivalent code | DIP14,.3 |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| power supply | 5 V |
| Maximum supply current (ICC) | 75 mA |
| programmable delay line | NO |
| Prop。Delay @ Nom-Sup | 50 ns |
| Certification status | Not Qualified |
| Maximum supply voltage (Vsup) | 5.25 V |
| Minimum supply voltage (Vsup) | 4.75 V |
| Nominal supply voltage (Vsup) | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | INDUSTRIAL |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
| Total delay nominal (td) | 50 ns |
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