4GB (x72, ECC, DR): 240-Pin DDR3 SDRAM VLP RDIMM
Features
DDR3 SDRAM VLP RDIMM
MT36JBZS51272P – 4GB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• DDR3 functionality and operations supported as
defined in the component data sheet
• 240-pin, very low profile registered dual in-line
memory module (VLP RDIMM)
• Compatible with ATCA form factors
• Fast data transfer rates: PC3-10600, PC3-12800,
PC3-8500, or PC3-6400
• 4GB (512 Meg x 72)
• Vdd = 1.5V ±0.075V
• Vddspd = +3.0V to +3.6V
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for
data and strobe signals
• Dual rank, using 2Gb TwinDie™ devices
• 8 internal device banks
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• On-board I
2
C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
• Gold edge contacts
• Lead-free
• Fly-by topology
• Terminated control, command, and address bus
Figure 1:
240-Pin VLP RDIMM
(ATCA-Compatible R/C N)
PCB height: 17.9mm (0.705in)
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
Options
• Operating temperature
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
• Package
–
240-pin DIMM (lead-free)
• Frequency/CAS latency
–
1.25ns @ CL = 11 (DDR3-1600)
–
1.5ns @ CL = 9 (DDR3-1333)
–
1.5ns @ CL = 10 (DDR3-1333)
2
–
1.87ns @ CL = 7 (DDR3-1066)
–
1.87ns @ CL = 8 (DDR3-1066)
2
–
2.5ns @ CL = 5 (DDR3-800)
2
–
2.5ns @ CL = 6 (DDR3-800)
2
1
Marking
None
I
Y
-1G6
-1G4
-1G3
-1G1
-1G0
-80C
-80B
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. Not recommended for new designs.
Table 1:
Speed
Grade
-1G6
-1G4
-1G3
-1G1
-1G0
-80C
-80B
Key Timing Parameters
Industry
Nomenclature
PC3-12800
PC3-10600
PC3-10600
PC3-8500
PC3-8500
PC3-6400
PC3-6400
Data Rate (MT/s)
CL = 11
1600
–
–
–
–
–
–
CL = 10
1333
1333
1333
–
–
–
–
CL = 9 CL = 8 CL = 7 CL = 6 CL = 5
–
1333
–
–
–
–
–
1066
1066
1066
1066
1066
–
–
–
1066
–
1066
–
–
–
800
800
800
800
800
800
800
–
–
–
–
–
800
–
t
RCD
(ns)
RP
(ns)
13.75
13.5
15
13.125
15
12.5
15
t
RC
(ns)
48.75
49.5
51
50.625
52.5
50
52.5
t
13.75
13.5
15
13.125
15
12.5
15
PDF: 09005aef8328da34/Source: 09005aef8328daed
JBZS36C512x72PY.fm - Rev. C 12/08 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
4GB (x72, ECC, DR): 240-Pin DDR3 SDRAM VLP RDIMM
Features
Table 2:
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
Addressing
4GB
8K
16K A[13:0]
8 BA[2:0]
2Gb TwinDie (512 Meg x 4)
2K A[11, 9:0]
2 S#[1:0]
Table 3:
Part Numbers and Timing Parameters – 4GB Modules
Base device: MT41J512M4THR,
1
2Gb DDR3 SDRAM
Module
Density
4GB
4GB
4GB
4GB
4GB
4GB
4GB
Module
Bandwidth
12.8 GB/s
10.6 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.25ns/1600 MT/s
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
11-11-11
9-9-9
10-10-10
7-7-7
8-8-8
5-5-5
6-6-6
Part Number
2
Configuration
512 Meg x 72
512 Meg x 72
512 Meg x 72
512 Meg x 72
512 Meg x 72
512 Meg x 72
512 Meg x 72
MT36JBZS51272P(I)Y-1G6__
MT36JBZS51272P(I)Y-1G4__
MT36JBZS51272P(I)Y-1G3__
MT36JBZS51272P(I)Y-1G1__
MT36JBZS51272P(I)Y-1G0__
MT36JBZS51272P(I)Y-80C__
MT36JBZS51272P(I)Y-80B__
Notes:
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes.
Example: MT36JBZS51272PY-1G1D1.
PDF: 09005aef8328da34/Source: 09005aef8328daed
JBZS36C512x72PY.fm - Rev. C 12/08 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, DR): 240-Pin DDR3 SDRAM VLP RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 4:
Pin Assignments
240-Pin DDR3 VLP RDIMM Front
240-Pin DDR3 VLP RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VrefDQ
Vss
DQ0
DQ1
Vss
DQS0#
DQS0
Vss
DQ2
DQ3
Vss
DQ8
DQ9
Vss
DQS1#
DQS1
Vss
DQ10
DQ11
Vss
DQ16
DQ17
Vss
DQS2#
DQS2
Vss
DQ18
DQ19
Vss
DQ24
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
DQ25
Vss
DQS3#
DQS3
Vss
DQ26
DQ27
Vss
CB0
CB1
Vss
DQS8#
DQS8
Vss
CB2
CB3
Vss
Vtt
Vtt
CKE0
Vdd
BA2
Err_Out#
Vdd
A11
A7
Vdd
A5
A4
Vdd
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
A2
Vdd
NF
NF
Vdd
Vdd
VrefCA
Par_In
Vdd
A10
BA0
Vdd
WE#
CAS#
Vdd
S1#
ODT1
Vdd
NC
Vss
DQ32
DQ33
Vss
DQS4#
DQS4
Vss
DQ34
DQ35
Vss
DQ40
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ41
Vss
DQS5#
DQS5
Vss
DQ42
DQ43
Vss
DQ48
DQ49
Vss
DQS6#
DQS6
Vss
DQ50
DQ51
Vss
DQ56
DQ57
Vss
DQS7#
DQS7
Vss
DQ58
DQ59
Vss
SA0
SCL
SA2
Vtt
121
Vss
151
Vss
181
A1
211
Vss
122
DQ4
152 DQS12 182
Vdd
212 DQS14
123
DQ5
153 DQS12# 183
Vdd
213 DQS14#
124
Vss
154
Vss
184
CK0
214
Vss
125
DQS9
155 DQ30 185
CK0#
215 DQ46
126 DQS9# 156 DQ31 186
Vdd
216 DQ47
127
Vss
157
Vss
187 EVENT# 217
Vss
128
DQ6
158
CB4
188
A0
218 DQ52
129
DQ7
159
CB5
189
Vdd
219 DQ53
130
Vss
160
Vss
190
BA1
220
Vss
131 DQ12 161 DQS17 191
Vdd
221 DQS15
132 DQ13 162 DQS17# 192
RAS#
222 DQS15#
133
Vss
163
Vss
193
S0#
223
Vss
134 DQS10 164
CB6
194
Vdd
224 DQ54
135 DQS10# 165
CB7
195 ODT0 225 DQ55
136
Vss
166
Vss
196
A13
226
Vss
137 DQ14 167
NC
197
Vdd
227 DQ60
138 DQ15 168 RESET# 198
NC
228 DQ61
139
Vss
169
CKE1
199
Vss
229
Vss
140 DQ20 170
Vdd
200 DQ36 230 DQS16
141 DQ21 171
A15
201 DQ37 231 DQS16#
142
Vss
172
A14
202
Vss
232
Vss
143 DQS11 173
Vdd
203 DQS13 233 DQ62
144 DQS11# 174
A12
204 DQS13# 234 DQ63
145
Vss
175
A9
205
Vss
235
Vss
146 DQ22 176
Vdd
206 DQ38 236 Vddspd
147 DQ23 177
A8
207 DQ39 237
SA1
148
Vss
178
A6
208
Vss
238
SDA
149 DQ28 179
Vdd
209 DQ44 239
Vss
150 DQ29 180
A3
210 DQ45 240
Vtt
PDF: 09005aef8328da34/Source: 09005aef8328daed
JBZS36C512x72PY.fm - Rev. C 12/08 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, DR): 240-Pin DDR3 SDRAM VLP RDIMM
Pin Assignments and Descriptions
Table 5:
Symbol
A[15:0]
Pin Descriptions
Type
Input
Description
Address inputs:
Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly”
during CAS commands. The address inputs also provide the op-code during the mode
register command set
.
A[13:0] address the 1Gb DDR3 devices. A[15:14] are needed to
calculate parity on the command/address bus.
Bank address inputs:
BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. BA[1:0] are used
as part of the parity calculation.
Clock:
CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM.
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DRAM. When enabled in normal operation, ODT is
only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be
ignored if disabled via the LOAD MODE command.
Parity input:
Parity bit for the address, RAS#, CAS#, and WE#.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
RESET# is an active LOW CMOS input referenced to Vss. The RESET# input receiver
is a CMOS input defined as a rail-to-rail signal with DC HIGH
≥
0.8 × Vdd and
DC LOW
≤
0.2 × Vdd.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs:
These pins are used to configure the temperature sensor/SPD
EEPROM address range on the I
2
C bus.
Serial clock for temperature sensor/SPD EEPROM:
SCL is used to synchronize
communication to and from the temperature sensor/SPD EEPROM.
Check bits:
Data used for ECC.
Data input/output:
Bidirectional data bus.
Data strobe:
DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out of
the temperature sensor/SPD EEPROM on the module on the I
2
C bus.
Parity error output:
Parity error found on the command and address bus.
BA[2:0]
Input
CK0, CK0#
Input
CKE[1:0]
ODT[1:0]
Input
Input
Par_In
RAS#, CAS#,
WE#
RESET#
Input
Input
Input
(LVCMOS)
Input
Input
Input
I/O
I/O
I/O
I/O
S#[1:0]
SA[2:0]
SCL
CB[7:0]
DQ[63:0]
DQS[17:0],
DQS#[17:0]
SDA
Err_Out#
EVENT#
Vdd
Vddspd
VrefCA
VrefDQ
Vss
Output
(open drain)
Output
Temperature event:
The EVENT# pin is asserted by the temperature sensor when critical
(open drain) temperature thresholds have been exceeded.
Supply
Power supply:
1.5V ±0.075V. The component Vdd and Vddq are connected to the
module Vdd.
Supply
Temperature sensor/SPD EEPROM power supply:
+3.0V to +3.6V.
Supply
Reference voltage:
Control, command, and address (Vdd/2).
Supply
Reference voltage:
DQ, DM (Vdd/2).
Supply
Ground.
PDF: 09005aef8328da34/Source: 09005aef8328daed
JBZS36C512x72PY.fm - Rev. C 12/08 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, DR): 240-Pin DDR3 SDRAM VLP RDIMM
Pin Assignments and Descriptions
Table 5:
Symbol
Vtt
NC
NF
Pin Descriptions (continued)
Type
Supply
–
–
Description
Termination voltage:
Used for control, command, and address (Vdd/2).
No connect:
These pins are not connected on the module.
No function:
Connected within the module, but provides no functionality.
PDF: 09005aef8328da34/Source: 09005aef8328daed
JBZS36C512x72PY.fm - Rev. C 12/08 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
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