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56F805: Description16-bit Hybrid Controller; File Size630KB，48 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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56F805 Overview

16-bit Hybrid Controller

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Freescale Semiconductor, Inc.

DSP56F805/D

Rev. 12.0, 02/2004

56F805

Technical Data

56F805 16-bit Hybrid Controller

•

Up to 40 MIPS at 80MHz core frequency

DSP and MCU functionality in a unified,

C-efficient architecture

Hardware DO and REP loops

MCU-friendly instruction set supports both

DSP and controller functions: MAC, bit

manipulation unit, 14 addressing modes

31.5K

16-bit words Program Flash

512

16-bit words Program RAM

16-bit words Data Flash

16-bit words Data RAM

16-bit words Boot Flash

PWM Outputs

Current Sense Inputs

Fault Inputs

PWM Outputs

Current Sense Inputs

Fault Inputs

A/D1

A/D2

VREF

ADC

Interrupt

Controller

•

Up to 64K

16-bit words each of external

Program and Data memory

Two 6-channel PWM Modules

Two 4-channel, 12-bit ADCs

Two Quadrature Decoders

CAN 2.0 B Module

Two Serial Communication Interfaces (SCIs)

Serial Peripheral Interface (SPI)

Up to four General Purpose Quad Timers

JTAG/OnCE

port for debugging

14 Dedicated and 18 Shared GPIO lines

144-pin LQFP Package

Freescale Semiconductor, Inc...

•

PWMA

RSTO

RESET

IRQA

EXTBOOT

IRQB

JTAG/

OnCE

Port

VPP

VCAPC V

Digital Reg

Analog Reg

DDA

SSA

PWMB

Low Voltage

Supervisor

Quadrature

Decoder 0/

Quad Timer A

Quadrature

Decoder 1/

Quad B Timer

Quad Timer C

Program Controller

and

Hardware Looping Unit

Address

Generation

Unit

Data ALU

16 x 16 + 36

→

36-Bit MAC

Three 16-bit Input Registers

Two 36-bit Accumulators

Bit

Manipulation

Unit

Program Memory

32252 x 16 Flash

512 x 16 SRAM

Boot Flash

2048 x 16 Flash

Data Memory

4096 x 16 Flash

2048 x 16 SRAM

•

PAB

•

PDB

•

IPBB

CONTROLS

Quad Timer D

/ Alt Func

CAN 2.0A/B

SCI0

GPIO

SCI1

GPIO

SPI

GPIO

Dedicated

GPIO

XDB2

CGDB

XAB1

XAB2

16-Bit

56800

Core

PLL

CLKO

XTAL

EXTAL

Clock Gen

•

INTERRUPT

CONTROLS

COP/

Watchdog

COP RESET

MODULE CONTROLS

ADDRESS BUS [8:0]

DATA BUS [15:0]

Application-

Specific

Memory &

Peripherals

IPBus Bridge

(IPBB)

External

Bus

Interface

Unit

External

Address Bus

Switch

External

Data Bus

Switch

Bus

Control

A[00:05]

PS Select

DS Select

WR Enable

RD Enable

A[06:15] or

GPIO-E2:E3 &

GPIO-A0:A7

D[00:15]

includes TCS pin which is reserved for factory use and is tied to VSS

Figure 1. 56F805 Block Diagram

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

56F805 Description

•

Two General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with four

pins

CAN 2.0 B Module with 2-pin port for transmit and receive

Two Serial Communication Interfaces, each with two pins (or four additional GPIO lines)

Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)

14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins

Computer Operating Properly (COP) watchdog timer

Two dedicated external interrupt pins

External reset input pin for hardware reset

External reset output pin for system reset

JTAG/On-Chip Emulation (OnCE™) module for unobtrusive, processor speed-independent

debugging

Software-programmable, Phase Locked Loop-based frequency synthesizer for the hybrid controller

core clock

Freescale Semiconductor, Inc...

•

1.1.4

•

Energy Information

Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

Uses a single 3.3V power supply

On-chip regulators for digital and analog circuitry to lower cost and reduce noise

Wait and Stop modes available

1.2 56F805 Description

The 56F805 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single

chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of

peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility,

and compact program code, the 56F805 is well-suited for many applications. The 56F805 includes many

peripherals that are especially useful for applications such as motion control, smart appliances, steppers,

encoders, tachometers, limit switches, power supply and control, automotive control, engine management,

noise suppression, remote utility metering, and industrial control for power, lighting, and automation.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming

model and optimized instruction set allow straightforward generation of efficient, compact code for both

MCU and DSP applications. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The 56F805 supports program execution from either internal or external memories. Two data operands can

be accessed from the on-chip Data RAM per instruction cycle. The 56F805 also provides two external

dedicated interrupt lines, and up to 32 General Purpose Input/Output (GPIO) lines, depending on

peripheral configuration.

The 56F805 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each

programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It

also supports program execution from external memory (64K).

56F805 Technical Data

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

The 56F805 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of field-

programmable software routines that can be used to program the main Program and Data Flash memory

areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page sizes of

256 words. The Boot Flash memory can also be either bulk- or page-erased.

Key application-specific features of the 56F805 include the two Pulse Width Modulator (PWM) modules.

These modules each incorporate three complementary, individually programmable PWM signal outputs

(each module is also capable of supporting six independent PWM functions for a total of 12 PWM outputs)

to enhance motor control functionality. Complementary operation permits programmable dead time

insertion, distortion correction via current sensing by software, and separate top and bottom output polarity

control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge-

and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is

capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC (Brush and

Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper motors.

The PWMs incorporate fault protection and cycle-by-cycle current limiting with sufficient output drive

capability to directly drive standard opto-isolators. A “smoke-inhibit”, write-once protection feature for

key parameters and a patented PWM waveform distortion correction circuit are also provided. Each PWM

is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from

1 to 16. The PWM modules provide a reference output to synchronize the ADCs.

The 56F805 incorporates two separate Quadrature Decoders capable of capturing all four transitions on the

two-phase inputs, permitting generation of a number proportional to actual position. Speed computation

capabilities accommodate both fast and slow moving shafts. The integrated watchdog timer in the

Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected.

Each input is filtered to ensure only true transitions are recorded.

This controller also provides a full set of standard programmable peripherals that include two Serial

Communications Interfaces (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of

these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. A

Controller Area Network interface (CAN Version 2.0 A/B-compliant), an internal interrupt controller and

14 dedicated GPIO are also included on the 56F805.

Freescale Semiconductor, Inc...

1.3 State of the Art Development Environment

•

Processor Expert

(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-

use component-based software application creation with an expert knowledge system.

The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,

compiling, and debugging. A complete set of evaluation modules (EVMs) and development system

cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a

complete, scalable tools solution for easy, fast, and efficient development.

For More Information On This Product,

Go to: www.freescale.com

56F805 Technical Data

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