TC74VHC9273P/FT/FK
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74VHC9273P,TC74VHC9273FT,TC74VHC9273FK
Octal D-Type Flip Flop with Clear
The TC74VHC9273 is an advanced high speed CMOS OCTAL
D-TYPE FLIP FLOP fabricated with silicon gate C
2
MOS
technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
Information signals applied to D inputs are transferred to the
Q outputs on the positive going edge of the clock pulse.
When the
CLR
input is held “L”, the Q outputs are at a low
logic level independent of the other inputs.
The
CLR
input and CK input have hysteresis between the
positive-going and negative-going thresholds. Thus the
TC74VHC9273 is capable of squaring up transitions of slowly
changing input signals and provides an improved noise
immunity.
It is easy to wire on the board because Input terminals are at
the opposite side of Output terminals.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
TC74VHC9273P
TC74VHC9273FT
TC74VHC9273FK
Features
•
•
•
•
•
•
•
•
High speed: f
max
= 195 MHz (typ.) at V
CC
= 5 V
Low power dissipation: I
CC
= 4
μA
(max) at Ta = 25°C
High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min)
Power down protection is provided on all inputs.
∼
Balanced propagation delays: t
pLH
−
t
pHL
Wide operating voltage range: V
CC (opr)
= 2 to 5.5 V
Function compatible with 74VHC273
Input terminals are at the opposite side of Output terminals
Weight
DIP20-P-300-2.54A
TSSOP20-P-0044-0.65A
VSSOP20-P-0030-0.50
: 1.30 g ( typ.)
: 0.08 g ( typ.)
: 0.03 g ( typ.)
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TC74VHC9273P/FT/FK
Absolute Maximum Ratings (Note1)
Characteristics
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC V
CC
/ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
Rating
−0.5
to 7.0
−0.5
to 7.0
−0.5
to V
CC
+ 0.5
−20
±20
±25
±75
500 (DIP) (Note 2)/180(TSSOP/VSSOP)
−65
to 150
Unit
V
V
V
mA
mA
mA
mA
mW
°C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta
= −40
to 65°C. From Ta
=
65 to 85°C a derating factor of
−10
mW/°C shall be
applied until 300 mW.
Operating Ranges (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Operating temperature
Symbol
V
CC
V
IN
V
OUT
T
opr
Rating
2.0 to 5.5
0 to 5.5
0 to V
CC
−40
to 85
Unit
V
V
V
°C
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either V
CC
or GND.
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TC74VHC9273P/FT/FK
AC Characteristics
(input: t
r
=
t
f
=
3 ns)
Characteristics
Symbol
Test Condition
V
CC
(V)
Propagation delay
time
(CK-Q)
3.3 ± 0.3
―
5.0 ± 0.5
C
L
(pF)
15
50
15
50
15
50
15
50
15
50
15
50
50
50
Min
―
―
―
―
―
―
―
―
85
50
130
80
―
―
―
(Note 2)
―
Ta = 25°C
Typ.
5.7
8.7
4.2
6.5
5.9
8.6
4.3
6.5
140
75
195
100
―
―
4
11
Max
11.8
18.4
7.7
12.1
12.3
18.0
8.0
11.9
―
―
―
―
1.5
1.0
10
―
Ta
= −
40 to
85°C
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
75
45
115
70
―
―
―
―
Max
13.4
20.9
8.8
13.8
14.0
20.6
9.1
13.6
―
―
―
―
1.5
1.0
10
―
ns
pF
pF
MHz
ns
ns
Unit
t
pLH
t
pHL
Propagation delay
time
( CLR -Q)
3.3 ± 0.3
t
pHL
―
5.0 ± 0.5
3.3 ± 0.3
Maximum clock
frequency
f
max
―
5.0 ± 0.5
t
osLH
t
osHL
C
IN
C
PD
3.3 ± 0.3
5.0 ± 0.5
―
Output to output skew
Input capacitance
Power dissipation
capacitance
(Note 1)
Note 1: Parameter guaranteed by design.
t
osLH
=
|t
pLHm
−
t
pLHn
|, t
osHL
=
|t
pHLm
−
t
pHLn
|
Note 2: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I
CC (opr)
=
C
PD
·V
CC
·f
IN
+
I
CC
/8 (per bit)
And the total C
PD
when n pcs.of flip flop operate can be calculated by the following equation:
C
PD
(total)
=
7
+
4·n
Input Equivalent Circuit
INPUT
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2009-04-01
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