IDT72V24110PFG datasheet, PDF - EEWORLD Datasheet

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IDT72V24110PFG: DescriptionFIFO, 4KX9, 6.5ns, Synchronous, CMOS, PQFP32, GREEN, PLASTIC, TQFP-32; Categorystorage storage; File Size137KB，14 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT72V24110PFG Overview

FIFO, 4KX9, 6.5ns, Synchronous, CMOS, PQFP32, GREEN, PLASTIC, TQFP-32

IDT72V24110PFG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	LQFP,
Contacts	32
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	6.5 ns
period time	10 ns
JESD-30 code	S-PQFP-G32
JESD-609 code	e3
length	7 mm
memory density	36864 bit
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	32
word count	4096 words
character code	4000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4KX9
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	7 mm

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3.3 VOLT CMOS SyncFIFO™

256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

4,096 x 9 and 8,192 x 9

IDT72V201, IDT72V211

IDT72V221, IDT72V231

IDT72V241, IDT72V251

FEATURES:

•

256 x 9-bit organization IDT72V201

512 x 9-bit organization IDT72V211

1,024 x 9-bit organization IDT72V221

2,048 x 9-bit organization IDT72V231

4,096 x 9-bit organization IDT72V241

8,192 x 9-bit organization IDT72V251

10 ns read/write cycle time

5V input tolerant

Read and Write clocks can be independent

Dual-Ported zero fall-through time architecture

Empty and Full Flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags can be set to

any depth

Programmable Almost-Empty and Almost-Full flags default to

Empty+7, and Full-7, respectively

Output Enable puts output data bus in high-impedance state

Advanced submicron CMOS technology

Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin

plastic Thin Quad FlatPack (TQFP)

Industrial temperature range (–40°C to +85°C) is available

Green parts available, see ordering information

DESCRIPTION:

The IDT72V201/72V211/72V221/72V231/72V241/72V251 SyncFIFOs™

are very high-speed, low-power First-In, First-Out (FIFO) memories with

clocked read and write controls. The architecture, functional operation and pin

assignments are identical to those of the IDT72201/72211/72221/72231/

72241/72251, but operate at a power supply voltage (Vcc) between 3.0V and

3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-bit

memory array, respectively. These FIFOs are applicable for a wide variety of

data buffering needs such as graphics, local area networks and interprocessor

communication.

These FIFOs have 9-bit input and output ports. The input port is

controlled by a free-running clock (WCLK), and two Write Enable pins

(WEN1, WEN2). Data is written into the Synchronous FIFO on every rising

clock edge when the Write Enable pins are asserted. The output port is

controlled by another clock pin (RCLK) and two Read Enable pins (REN1,

REN2).

The Read Clock can be tied to the Write Clock for single clock

operation or the two clocks can run asynchronous of one another for dual-

clock operation. An Output Enable pin (OE) is provided on the read port

for three-state control of the output.

The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF).

Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are

provided for improved system control. The programmable flags default to

Empty+7 and Full-7 for

PAE

and

PAF,

respectively. The programmable flag

offset loading is controlled by a simple state machine and is initiated by asserting

the Load pin (LD).

These FIFOs are fabricated using IDT's high-speed submicron CMOS

technology.

FUNCTIONAL BLOCK DIAGRAM

WCLK

WEN1

WEN2

INPUT REGISTER

OFFSET REGISTER

PAE

PAF

- D

WRITE CONTROL

LOGIC

RAM ARRAY

256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

4,096 x 9, 8,192 x 9

FLAG

LOGIC

WRITE POINTER

READ POINTER

READ CONTROL

LOGIC

OUTPUT REGISTER

RESET LOGIC

RCLK

REN1

REN2

- Q

4092 drw 01

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

FEBRUARY 2006

DSC-4092/4

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