16 Megabit High Speed CMOS SRAM
DPS1MX16MKn3
SLCC Stack
DESCRIPTION:
The DPS1MX16MKn3 High Speed SRAM ‘’STACK’’ modules are a
revolutionary new memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC).
Available in straight leaded, ‘’J’’ leaded or gullwing leaded
packages. The module packs 16-Megabits of low-power CMOS
static RAM in an area as small as 0.549 in
2
, while maintaining a
total height as low as 0.269 inches.
The DPS1MX16MKn3 STACK modules contain four individual
512K x 8 SRAMs, each packaged in a hermetically sealed SLCC,
making the modules suitable for commercial, industrial and
military applications.
By using SLCCs, the ‘’Stack’’ family of modules offer a higher board
density of memory than available with conventional through-hole,
surface mount or hybrid techniques.
Straight
Leaded
Stack
FEATURES:
•
Organizations Available:
•
•
•
•
•
•
•
1Meg x 16 or 2 Meg x 8
Access Times: 20*, 25, 30, 35, 45ns
Fully Static Operation
- No clock or refresh required
Single +5V Power Supply,
±
10% Tolerance
TTL Compatible
Common Data Inputs and Outputs
Low Data Retention Voltage:
2.0V min.
Packages Available:
SLCC Stack
Straight Leaded Stack
‘’J’’ Leaded Stack
Gullwing Leaded Stack
‘’J’’ Leaded
Stack
Gullwing
Leaded
Stack
*
Commercial and Industrial Grade only.
FUNCTIONAL BLOCK DIAGRAM
PIN NAMES
A0 - A18
I/O0 - I/O15
CE0 - CE3
WE
OE0, OE1
V
DD
V
SS
N.C.
30A129-04
REV. E
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
Address Inputs
Data Input/Output
Low Chip Enables
Write Enable
Output Enables
Power (+5V)
Ground
No Connect
1
DPS1MX16MKn3
PIN-OUT DIAGRAM
Mode
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
Dense-Pac Microsystems, Inc.
TRUTH TABLE
CE
H
L
L
L
WE
X
H
H
L
L = LOW
OE
X
H
L
X
Supply
I/O Pin Current
High-Z Standby
High-Z Active
D
OUT
Active
D
IN
Active
X = Don’t Care
3
ABSOLUTE MAXIMUM RATINGS
Symbol
T
STC
T
BIAS
V
DD
V
I/O
Parameter
Value
Storage Temperature
-65 to +150
Temperature Under Bias
-55 to +125
1
Supply Voltage
-0.5 to +7.0
1
Input/Output Voltage
-0.5 to V
DD
+0.5
3
Unit
°C
°C
°C
V
RECOMMENDED OPERATING RANGE
Symbol
Characteristic
V
DD
Supply Voltage
V
IH
Input HIGH Voltage
V
IL
Input LOW Voltage
M/B
Operating
T
A
I
Temperature
C
Min.
4.5
2.2
-0.5
2
-55
-40
0
Typ.
5.0
CAPACITANCE
4
: T
A
= 25
°
C, F = 1.0MHz
Symbol
C
ADR
C
CE
C
WE
C
OE
C
I/O
Parameter
Address Input
Chip Enable
Write Enable
Output Enable
Data Input/Output
Max.
40
16
40
25
25
Unit
Condition
Max. Unit
5.5
V
V
DD
+0.3 V
0.8
V
+25 +125
o
+25
+85
C
+25
+70
DC OUTPUT CHARACTERISTICS
pF
V
IN2
=
0V
Symbol
Parameter
V
OH
HIGH Voltage
V
OL
LOW Voltage
Conditions Min. Max. Unit
I
OH
= -4.0mA 2.4
V
I
OL
=8.0mA
0.4
V
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
I
DR3
I
DR2
V
OL
V
OH
Characteristics
Input
Leakage Current
Output
Leakage Current
Operating
Supply Current
Full Standby
Supply Current
Standby Current (TTL)
Data Retention
Supply Current (3.0V)
Data Retention
Supply Current (2.0V)
Output Low Voltage
Output High Voltage
Test Conditions
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD
,
CE or OE = V
IH
, or WE = V
IL
Cycle=min., Duty=100% X8
I
OUT
= 0mA
X16
V
IN
≥
V
DD
-0.2V or
V
IN
≤
V
SS
+0.2V
CE = V
IH
V
DR
= 3.0V, CE
≥
V
DR
-0.2V
V
DR
= 2.0V, CE
≥
V
DR
-0.2V
I
OUT
= 8.0mA
I
OUT
= -4.0mA
Typ.
(†)
-
-
185
290
4
80
0.6
0.4
-
-
2.4
C
Min.
Max.
Min.
I
Max.
M/B
Min.
Max.
Unit
µA
µA
mA
mA
mA
mA
mA
V
V
-20
-20
+20
+20
350
460
40
240
2.0
1.2
0.4
-20
-20
+20
+20
360
480
40
240
4.0
3.2
0.4
-20
-20
+20
+20
36 0
480
60
240
8.0
7.2
0.4
2.4
2.4
† Typical measurements made at +25
o
C, Cycle = min., V
DD
= 5.0V.
2
30A129-04
REV. E
Dense-Pac Microsystems, Inc.
DPS1MX16MKn3
Figure 1. Output Load
+5V
480Ω
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
0V to 3.0V
5ns
1.5V
OUTPUT LOAD
Load
1
2
C
L
100pF
5pF
Parameters Measured
except t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
D
OUT
C
L
*
255Ω
Data Retention AC Characteristics
8
Symbol
V
DR
V
CDR
t
R
Parameter
V
DD
for Data Retention
Chip Disable to
Data Retention Time
Operation Recovery Time
Test Conditions
CE
≥
V
DR
-0.2V
See Data Retention Waveform
See Data Retention Waveform
Min.
2.0
0
5
Typ.
-
-
-
Max.
-
-
-
Unit
V
ns
ms
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
Over operating ranges
No. Symbol
1
2
3
4
5
6
7
8
9
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
Parameter
Read Cycle Time
Address Access Time
CE to Output Valid
Output Enable to Output Valid
CE to Output in LOW-Z
4, 5
Output Enable to Output in LOW-Z
4, 5
CE to Output in HIGH-Z
4, 5
Output Enable to Output in HIGH-Z
4, 5
Output Hold from Address Change
20ns*
Min.
Max.
25ns
Min.
Max.
30ns
Min.
Max.
35ns
Min.
Max.
45ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
20
10
3
0
0
4
8
8
25
25
25
12
3
0
0
5
10
10
30
30
30
15
3
0
0
5
15
15
35
35
35
20
3
0
0
5
20
20
45
45
45
25
3
0
0
5
25
25
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE
6, 7
:
Over operating ranges
No. Symbol
10
11
12
13
14
15
16
17
18
19
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Parameter
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-Up Time **
Write Pulse Width
Write Recovery Time
Write Enable to Output in HIGH-Z
4, 5
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
20ns*
Min.
Max.
25ns
Min.
Max.
30ns
Min.
Max.
35ns
Min.
Max.
45ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
13
13
0
13
0
0
9
0
3
8
25
15
15
0
15
0
0
10
0
3
10
30
20
20
0
20
0
0
12
0
3
12
35
25
25
0
25
0
0
15
0
3
15
45
35
35
0
35
0
0
20
0
3
20
* Available in Commercial and Industrial Grade Only.
** Valid for both Read and Write Cycles.
30A129-04
REV. E
3
DPS1MX16MKn3
Dense-Pac Microsystems, Inc.
DATA RETENTION WAVEFORM:
CE Controlled.
V
DD
4.5V
2.3V
V
DR1
CE
0V
CE
≥
V
DD
-0.2V
READ CYCLE
ADDRESS
CE
OE
DATA I/O
WRITE CYCLE 1:
CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
4
30A129-04
REV. E
Dense-Pac Microsystems, Inc.
DPS1MX16MKn3
WRITE CYCLE 2:
WE Controlled. OE is HIGH.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 3:
WE Controlled. OE is LOW.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
30A129-04
REV. E
5
京公网安备 11010802033920号
EEWORLD
