Am29F040B
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
21445
Revision
E
Amendment
1
Issue Date
October 5, 2004
Am29F040B
4 Megabit (512 K x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector
Flash Memory
Distinctive Characteristics
5.0 V
±
10% for read and write operations
— Minimizes system level power requirements
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes
and verifies bytes at specified addresses
Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29F040 device
High performance
— Access times as fast as 55 ns
Low power consumption
— 20 mA typical active read current
— 30 mA typical program/erase current
— 1 µA typical standby current (standard access time to
active mode)
Minimum 1,000,000 program/erase cycles
per sector guaranteed
20-year data retention at 125°C
— Reliable operation for the life of the system
Package options
— 32-pin PLCC, TSOP, or PDIP
Flexible sector architecture
— 8 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased
— Supports full chip erase
— Sector protection:
Compatible with JEDEC standards
— Pinout and software compatible with single-power-
supply Flash standard
— Superior inadvertent write protection
Data# Polling and toggle bits
— Provides a software method of detecting program or
erase cycle completion
A hardware method of locking sectors to prevent
any program or erase operations within that sector
Erase Suspend/Erase Resume
— Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then
resumes the erase operation
This Data Sheet states AMD’s current technical specifications regarding the Products described
herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in
technical specifications.
Publication#
21445
Rev:
E
Amendment/1
Issue Date:
October 5, 2004
General Description
The Am29F040B is a 4 Mbit, 5.0 volt-only Flash
memory organized as 524,288 Kbytes of 8 bits
each. The 512 Kbytes of data are divided into
eight sectors of 64 Kbytes each for flexible erase
c a p a b i l i ty. T h e 8 b i ts o f d a t a a p p e a r on
DQ0–DQ7. The Am29F040B is offered in 32-pin
PLCC, TSOP, and PDIP packages. This device is
designed to be programmed in-system with the
standard system 5.0 volt V
CC
supply. A 12.0 volt
V
PP
is not required for write or erase operations.
The device can also be programmed in standard
EPROM programmers.
This device is manufactured using AMD’s 0.32
µm process technology, and offers all the fea-
tures and benefits of the Am29F040, which was
manufactured using 0.5 µm process technology.
In addtion, the Am29F040B has a second toggle
bit, DQ2, and also offers the ability to program
in the Erase Suspend mode.
The standard Am29F040B offers access times of
55, 70, 90, 120, and 150 ns, allowing
high-speed microprocessors to operate without
wait states. To eliminate bus contention the de-
vice has separate chip enable (CE#), write
enable (WE#) and output enable (OE#)
controls.
The device requires only a
single 5.0 volt
power supply
for both read and write func-
tions. Internally generated and regulated
voltages are provided for the program and erase
operations.
The device is entirely command set compatible
with the
JEDEC single-power-supply Flash
standard.
Commands are written to the com-
mand register using standard microprocessor
write timings. Register contents serve as input
to an internal state-machine that controls the
erase and programming circuitry. Write cycles
also internally latch addresses and data needed
for the programming and erase operations.
Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
Device programming occurs by executing the
program command sequence. This initiates the
Embedded Program
algorithm—an internal al-
gorithm that automatically times the program
pulse widths and verifies proper cell margin.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embed-
ded Erase
algorithm—an internal algorithm
that automatically preprograms the array (if it is
not already programmed) before executing the
erase operation. During erase, the device auto-
matically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program
or erase operation is complete by reading the
DQ7 (Data# Polling) and DQ6 (toggle)
status
bits.
After a program or erase cycle has been
completed, the device is ready to read array
data or accept another command.
The
sector erase architecture
allows memory
sectors to be erased and reprogrammed without
affecting the data contents of other sectors. The
device is fully erased when shipped from the
factory.
Hardware data protection
measures include
a low V
CC
detector that automatically inhibits
write operations during power transitions. The
hardware sector protection
feature disables
both program and erase operations in any com-
bination of the sectors of memory. This can be
achieved via programming equipment.
The
Erase Suspend
feature enables the user to
put erase on hold for any period of time to read
data from, or program data to, any sector that
is not selected for erasure. True background
erase can thus be achieved.
The system can place the device into the
standby
mode.
Power consumption is greatly reduced in
this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce
the highest levels of quality, reliability and cost
effectiveness. The device electrically erases all
bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is pro-
grammed using hot electron injection.
2
Am29F040B
Table of Contents
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29F040B Device Bus Operations .................................10
Figure 6. Maximum Positive Overshoot Waveform........................ 22
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
TTL/NMOS Compatible .......................................................... 23
CMOS Compatible.................................................................. 23
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7. Test Setup...................................................................... 24
Table 6. Test Specifications ........................................................... 24
Requirements for Reading Array Data ...................................
Writing Commands/Command Sequences ............................
Program and Erase Operation Status ....................................
Standby Mode ........................................................................
Output Disable Mode..............................................................
10
10
11
11
11
Key to Switching Waveforms. . . . . . . . . . . . . . . . 24
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Read Only Operations ............................................................ 25
Figure 8. Read Operation Timings ................................................. 25
Erase and Program Operations .............................................. 26
Figure 9. Program Operation Timings............................................
Figure 10. Chip/Sector Erase Operation Timings ..........................
Figure 11. Data# Polling Timings (During Embedded Algorithms).
Figure 12. Toggle Bit Timings (During Embedded Algorithms)......
Figure 13. DQ2 vs. DQ6.................................................................
27
27
28
28
29
Table 2. Sector Addresses Table ....................................................11
Autoselect Mode..................................................................... 12
Table 3. Am29F040B Autoselect Codes (High Voltage Method) .....12
Sector Protection/Unprotection............................................... 12
Hardware Data Protection ...................................................... 12
Low V
CC
Write Inhibit ...................................................................... 12
Write Pulse “Glitch” Protection ........................................................ 13
Logical Inhibit .................................................................................. 13
Power-Up Write Inhibit .................................................................... 13
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30
Erase and Program Operations .............................................. 30
Alternate CE# Controlled Writes .................................................... 30
Figure 14. Alternate CE# Controlled Write Operation Timings ...... 31
Command Definitions . . . . . . . . . . . . . . . . . . . . . 13
Reading Array Data ................................................................ 13
Reset Command..................................................................... 13
Autoselect Command Sequence ............................................ 13
Byte Program Command Sequence....................................... 14
Figure 1. Program Operation .......................................................... 14
Chip Erase Command Sequence ........................................... 14
Sector Erase Command Sequence ........................................ 15
Erase Suspend/Erase Resume Commands........................... 15
Figure 2. Erase Operation............................................................... 16
Command Definitions ............................................................. 16
Table 4. Am29F040B Command Definitions....................................16
Write Operation Status . . . . . . . . . . . . . . . . . . . . 18
DQ7: Data# Polling................................................................. 18
Figure 3. Data# Polling Algorithm ................................................... 18
DQ6: Toggle Bit I ....................................................................
DQ2: Toggle Bit II ...................................................................
Reading Toggle Bits DQ6/DQ2 ..............................................
DQ5: Exceeded Timing Limits ................................................
DQ3: Sector Erase Timer .......................................................
19
19
19
20
20
Figure 4. Toggle Bit Algorithm......................................................... 20
Table 5. Write Operation Status.......................................................21
Erase and Programming Performance . . . . . . . . 32
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 32
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 32
PLCC and PDIP Pin Capacitance. . . . . . . . . . . . . 33
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 34
PD 032—32-Pin Plastic DIP ................................................... 34
PL 032—32-Pin Plastic Leaded Chip Carrier ......................... 35
TS 032—32-Pin Standard Thin Small Package...................... 36
TSR032—32-Pin Reversed Thin Small Outline Package....... 37
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 38
Revision A (May 1997) ........................................................... 38
Revision B (January 1998) ..................................................... 38
Revision B+1 (January 1998) ................................................. 38
Revision B+2 (April 1998)....................................................... 38
Revision C (January 1999) ..................................................... 38
Distinctive Characteristics....................................................... 38
Revision C+1 (February 1999) ............................................... 38
Revision C+2 (May 17, 1999) ................................................. 38
Revision D (November 15, 1999) ........................................... 38
Revision E0 (November 29, 2000).......................................... 38
Revision E1 (September 21, 2004)......................................... 38
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 22
Figure 5. Maximum Negative Overshoot Waveform ....................... 22
Am29F040B
3
Microcontroller MCU
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