HYMD116725BL8J-J datasheet, PDF

Datasheet> All Categories > storage> storage> HYMD116725BL8J-J

HYMD116725BL8J-J: DescriptionUnbuffered DDR SDRAM DIMM; Categorystorage storage; File Size228KB，16 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

Download Datasheet Parametric View All

HYMD116725BL8J-J Overview

Unbuffered DDR SDRAM DIMM

HYMD116725BL8J-J Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	SK Hynix
Parts packaging code	DIMM
package instruction	DIMM, DIMM184
Contacts	184
Reach Compliance Code	compli
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.7 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N184
memory density	1207959552 bi
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	184
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM184
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	4096
self refresh	YES
Maximum standby current	0.18 A
Maximum slew rate	2.7 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

Preview

Download Datasheet

View All

16Mx72 bits

Unbuffered DDR SDRAM DIMM

HYMD116725B(L)8J-J

DESCRIPTION

Hynix HYMD116725B(L)8J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory

Modules (DIMMs) which are organized as 16Mx72 high-speed memory arrays. Hynix HYMD116725B(L)8J-J series

consists of nine 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix

HYMD116725B(L)8J-J series provide a high performance 8-byte interface in 5.25" width form factor of industry stan-

dard. It is suitable for easy interchange and addition.

Hynix HYMD116725B(L)8J-J series is designed for high speed of up to 166MHz and offers fully synchronous opera-

tions referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are

latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising

and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All

input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and

burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD116725B(L)8J-J series incorporates SPD(serial presence detect). Serial presence detect function is

implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify

DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

•

128MB (16M x 72) Unbuffered DDR DIMM based on

16Mx8 DDR SDRAM

JEDEC Standard 184-pin dual in-line memory mod-

ule (DIMM)

Error Check Correction (ECC) Capability

2.5V +/- 0.2V VDD and VDDQ Power supply

All inputs and outputs are compatible with SSTL_2

interface

Fully differential clock operations (CK & /CK) with

100MHz/125MHz/133MHz/166MHz

All addresses and control inputs except Data, Data

strobes and Data masks latched on the rising edges

of the clock

•

Data(DQ), Data strobes and Write masks latched on

both rising and falling edges of the clock

Data inputs on DQS centers when write (centered

DQ)

Data strobes synchronized with output data for read

and input data for write

Programmable CAS Latency 2 / 2.5 supported

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

tRAS Lock-out function supported

Internal four bank operations with single pulsed RAS

Auto refresh and self refresh supported

ORDERING INFORMATION

Part No.

HYMD116725B(L)8J-J

Power Supply

=2.5V

DDQ

=2.5V

Clock Frequency

166MHz (*DDR333)

Interface

SSTL_2

Form Factor

184pin Unbuffered DIMM

5.25 x 1.25 x 0.15 inch

* JEDEC Defined Specifications compliant

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.2/Jun. 02

Recommended Resources

Electric iron circuit

Constant current source circuit

μPC1318AV power amplifier circuit diagram

Circuit diagram of a regulated power supply composed of thyristors with an output of 12V-30V and 20A

CMOS multipoint timer

Remote single wire control motor circuit

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components