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HY5DU573222AFM: Description256M(8Mx32) GDDR SDRAM; File Size655KB，30 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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256M(8Mx32) GDDR SDRAM

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HY5DU573222AFM

256M(8Mx32) GDDR SDRAM

HY5DU573222AFM

This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any respon-

sibility for use of circuits described. No patent licenses are implied.

Rev. 0.5 / Aug. 2003

HY5DU573222AFM

PIN DESCRIPTION

CK, /CK

TYPE

Input

DESCRIPTION

Clock: CK and /CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of /CK. Output

(read) data is referenced to the crossings of CK and /CK (both directions of crossing).

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER

DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row

ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF

REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE

must be maintained high throughout READ and WRITE accesses. Input buffers, excluding

CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are

disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW

level after Vdd is applied.

Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-

mands are masked when CS0 or CS1 is registered high. CS0 or CS1 provides for external

bank selection on systems with multiple banks. CS0 and CS1 are considered part of the

command code. When it is the operationg state of MRS, Power up sequence, EMRS, it

should be enabled in pairs. Except this case, it can be operated, individually.

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-

CHARGE command is being applied.

Address Inputs: Provide the row address for ACTIVE commands, and the column address

and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the

memory array in the respective bank. A8 is sampled during a precharge command to

determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8

HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The

address inputs also provide the op code during a MODE REGISTER SET command. BA0

and BA1 define which mode register is loaded during the MODE REGISTER SET command

(MRS or EMRS).

Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being

entered.

Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with that input data during a WRITE access. DM is sam-

pled on both edges of DQS. Although DM pins are input only, the DM loading matches the

DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the

data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the

data on DQ24-Q31.

Data Strobe: Output with read data, input with write data. Edge aligned with read data,

centered in write data. Used to capture write data. DQS0 corresponds to the data on

DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on

DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31

Data input / output pin : Data Bus

Power supply for internal circuits and input buffers.

Power supply for output buffers for noise immunity.

Reference voltage for inputs for SSTL interface.

No connection.

CKE

Input

/CS0, /CS1

Input

BA0, BA1

Input

A0 ~ A11

Input

/RAS, /CAS, /WE

Input

DM0 ~ DM3

Input

DQS0 ~ DQS3

I/O

DQ0 ~ DQ31

DDQ

SSQ

REF

I/O

Supply

Rev. 0.5 / Aug. 2003

HY5DU573222AFM Related Products

	HY5DU573222AFM	HY5DU573222AFM-25	HY5DU573222AFM-33	HY5DU573222AFM-36	HY5DU573222AFM-28	HY5DU573222AFM-4
Description	256M(8Mx32) GDDR SDRAM	256M(8Mx32) GDDR SDRAM	256M(8Mx32) GDDR SDRAM	256M(8Mx32) GDDR SDRAM	256M(8Mx32) GDDR SDRAM	256M(8Mx32) GDDR SDRAM
Is it Rohs certified?	-	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	-	SK Hynix	SK Hynix	SK Hynix	SK Hynix	SK Hynix
Parts packaging code	-	BGA	BGA	BGA	BGA	BGA
package instruction	-	LFBGA, BGA144,12X12,32	LFBGA, BGA144,12X12,32	LFBGA, BGA144,12X12,32	LFBGA, BGA144,12X12,32	LFBGA, BGA144,12X12,32
Contacts	-	144	144	144	144	144
Reach Compliance Code	-	unknow	unknow	unknow	unknow	unknow
ECCN code	-	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	-	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	-	0.6 ns	0.6 ns	0.6 ns	0.6 ns	0.6 ns
Other features	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	-	400 MHz	300 MHz	277 MHz	357 MHz	250 MHz
I/O type	-	COMMON	COMMON	COMMON	COMMON	COMMON
interleaved burst length	-	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8
JESD-30 code	-	S-PBGA-B144	S-PBGA-B144	S-PBGA-B144	S-PBGA-B144	S-PBGA-B144
length	-	12 mm	12 mm	12 mm	12 mm	12 mm
memory density	-	268435456 bi	268435456 bi	268435456 bi	268435456 bi	268435456 bi
Memory IC Type	-	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	-	32	32	32	32	32
Number of functions	-	1	1	1	1	1
Number of ports	-	1	1	1	1	1
Number of terminals	-	144	144	144	144	144
word count	-	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words
character code	-	8000000	8000000	8000000	8000000	8000000
Operating mode	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	-	70 °C	70 °C	70 °C	70 °C	70 °C
organize	-	8MX32	8MX32	8MX32	8MX32	8MX32
Output characteristics	-	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA
Encapsulate equivalent code	-	BGA144,12X12,32	BGA144,12X12,32	BGA144,12X12,32	BGA144,12X12,32	BGA144,12X12,32
Package shape	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	-	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	-	2.8 V	2.5 V	2.5 V	2.8 V	2.5 V
Certification status	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	-	4096	4096	4096	4096	4096
Maximum seat height	-	1.4 mm	1.4 mm	1.4 mm	1.4 mm	1.4 mm
self refresh	-	YES	YES	YES	YES	YES
Continuous burst length	-	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8
Maximum standby current	-	0.07 A	0.05 A	0.05 A	0.06 A	0.05 A
Maximum slew rate	-	1.1 mA	0.82 mA	0.72 mA	0.95 mA	0.72 mA
Maximum supply voltage (Vsup)	-	2.95 V	2.625 V	2.625 V	2.95 V	2.625 V
Minimum supply voltage (Vsup)	-	2.55 V	2.2 V	2.375 V	2.55 V	2.375 V
Nominal supply voltage (Vsup)	-	2.8 V	2.5 V	2.5 V	2.8 V	2.5 V
surface mount	-	YES	YES	YES	YES	YES
technology	-	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	-	BALL	BALL	BALL	BALL	BALL
Terminal pitch	-	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	-	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	-	12 mm	12 mm	12 mm	12 mm	12 mm

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Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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