HY5S5B2CLFP-SE datasheet, PDF - EEWORLD Datasheet

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HY5S5B2CLFP-SE: Description256M (8Mx32bit) Mobile SDRAM; Categorystorage storage; File Size1MB，54 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

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HY5S5B2CLFP-SE Overview

256M (8Mx32bit) Mobile SDRAM

HY5S5B2CLFP-SE Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SK Hynix
Parts packaging code	BGA
package instruction	VFBGA, BGA90,9X15,32
Contacts	90
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	7 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	105 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PBGA-B90
JESD-609 code	e1
length	13 mm
memory density	268435456 bi
Memory IC Type	SYNCHRONOUS DRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	90
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	8MX32
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA90,9X15,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.0003 A
Maximum slew rate	0.06 mA
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	8 mm

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256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O

Specification of

256M (8Mx32bit) Mobile SDRAM

Memory Cell Array

- Organized as 4banks of 2,097,152 x32

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 1.5 / Aug. 2008

256Mbit (8Mx32bit) Mobile SDR Memory

HY5S5B2CLF(P) Series

DESCRIPTION

The Hynix HY5S5B2CLF(P) is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular

phones with internet access and multimedia capabilities, mini-notebook, hand-held PCs.

The Hynix 256M Mobile SDRAM is 268,435,456-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the

main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of

2,097,152 x32.

Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch

each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the

input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16 Input/

Output bus. All the commands are latched in synchronization with the rising edge of CLK.

The Mobile SDRAMs provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8

locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is ini-

tiated at the end of the burst access. The Mobile SDRAM uses an internal pipelined architecture to achieve high-speed

operation. This architecture is compatible with the

rule of prefetch architectures, but it also allows the column

address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while

accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-

access operation.

Read and write accesses to the Hynix Mobile SDRAMs are burst oriented;

accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.

The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be

accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and

the starting column location for the burst access. A burst of Read or Write cycles in progress can be terminated by a

burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any

cycle(This pipelined design is not restricted by a

rule).

The Hynix Mobile SDR also provides for special programmable options including Partial Array Self Refresh of full array,

half array, quarter array, Temperature Compensated Self Refresh of 45 or 85 degrees

The Hynix Mobile SDR has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh) to

reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automatically

adjust refresh rate according to temperature without external EMRS command.

Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power

reduction by removing power to the memory array within each Mobile SDR. By using this feature, the system can cut

off almost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout

flexibility.

All inputs are LV-CMOS compatible. Devices will have a V

and V

DDQ

supply of 1.8V (nominal).

Rev 1.5 / Aug. 2008

HY5S5B2CLFP-SE Related Products

	HY5S5B2CLFP-SE	HY5S5B2CLFP-6E
Description	256M (8Mx32bit) Mobile SDRAM	256M (8Mx32bit) Mobile SDRAM
Is it Rohs certified?	conform to	conform to
Maker	SK Hynix	SK Hynix
Parts packaging code	BGA	BGA
package instruction	VFBGA, BGA90,9X15,32	VFBGA, BGA90,9X15,32
Contacts	90	90
Reach Compliance Code	unknow	unknow
ECCN code	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	7 ns	5.4 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	105 MHz	166 MHz
I/O type	COMMON	COMMON
interleaved burst length	1,2,4,8	1,2,4,8
JESD-30 code	R-PBGA-B90	R-PBGA-B90
JESD-609 code	e1	e1
length	13 mm	13 mm
memory density	268435456 bi	268435456 bi
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	32	32
Number of functions	1	1
Number of ports	1	1
Number of terminals	90	90
word count	8388608 words	8388608 words
character code	8000000	8000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-25 °C	-25 °C
organize	8MX32	8MX32
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VFBGA	VFBGA
Encapsulate equivalent code	BGA90,9X15,32	BGA90,9X15,32
Package shape	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	260
power supply	1.8 V	1.8 V
Certification status	Not Qualified	Not Qualified
refresh cycle	4096	4096
Maximum seat height	1 mm	1 mm
self refresh	YES	YES
Continuous burst length	1,2,4,8,FP	1,2,4,8,FP
Maximum standby current	0.0003 A	0.0003 A
Maximum slew rate	0.06 mA	0.065 mA
Maximum supply voltage (Vsup)	1.95 V	1.95 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	OTHER	OTHER
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	20	20
width	8 mm	8 mm

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