256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O
Document Title
4Bank x 4M x 16bits Synchronous DRAM
Revision History
Revision No.
0.1
0.2
0.3
1.0
Initial Draft
Modification of IDD Current
Modification of IDD3P & IDD3PS
IDD3P / IDD3PS : 3mA / 2mA --> 5mA / 5mA
Final revision
History
Draft Date
Aug. 2004
Oct. 2004
Jan. 2005
Jul. 2005
Remark
Preliminary
Preliminary
Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.0 / Jul. 2005
1
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256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
DESCRIPTION
The Hynix Low Power SDRAM(Mobile SDR) is suited for non-PC application which use the batteries such as PDAs, 2.5G
and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.
The Hynix HY5S5B6ELF(P) is a 268,435,456bit CMOS Synchronous Dynamic Random Access Memory. It is organized
as 4banks of 4,194,304x16.
The Low Power SDRAM(Mobile SDR) provides for programmable options including CAS latency of 1, 2, or 3, READ or
WRITE burst length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Low
Power SDRAM(Mobile SDR) also provides for special programmable options including Partial Array Self Refresh of a
quarter bank, a half bank, 1bank, 2banks, or all banks.
The Hynix HY5S5B6ELF(P) has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh)
to reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automati-
cally adjust refresh rate according to temperature without external EMRS command. A burst of Read or Write cycles in
progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or
Write command on any cycle(This pipelined design is not restricted by a 2N rule).
Deep Power Down Mode is a additional operating mode for Low Power SDRAM(Mobile SDR). This mode can achieve
maximum power reduction by removing power to the memory array within each SDRAM. By using this feature, the sys-
tem can cut off alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-
line layout flexibility.
FEATURES
Standard SDRAM Protocol
●
●
Programmable CAS latency of 1, 2 or 3
-25
o
C ~ 85
o
C Operation
Package Type
: 54ball, 0.8mm pitch FBGA (Lead Free, Lead)
Internal 4bank operation
Power Supply Voltage : V
DD
= 1.8V, V
DDQ
= 1.8V
LVCMOS compatible I/O Interface
Low Voltage interface to reduce I/O power
●
●
●
●
- HY5S5B6ELFP : Lead Free
- HY5S5B6ELF : Lead
●
●
Low Power Features
- PASR(Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- DS (Drive Strength)
- Deep Power Down Mode
256M SDRAM ORDERING INFORMATION
Part Number
HY5S5B6ELF-HE
HY5S5B6ELF-SE
HY5S5B6ELFP-HE
HY5S5B6ELFP-SE
Clock Frequency
133MHz
105MHz
133MHz
105MHz
CAS Latency
3
3
3
3
4banks x 4Mb x 16
LVCMOS
Lead Free
Organization
Interface
54Ball FBGA
Lead
Rev 1.0 / Jul. 2005
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1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
BALL DESCRIPTION
Ball Out
F2
SYMBOL
CLK
TYPE
INPUT
DESCRIPTION
Clock : The system clock input. All other inputs are registered to the
SDRAM on the rising edge of CLK
Clock Enable : Controls internal clock signal and when deactivated, the
SDRAM will be one of the states among (deep) power down, suspend or
self refresh
Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and
LDQM
Bank Address : Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask : Controls output buffers in read mode and masks input data
in write mode
F3
CKE
INPUT
G9
G7,G8
H7, H8, J8, J7,
J3, J2, H3, H2,
H1, G1, G3,
H9, G2
F8, F7, F9
F1, E8
A8, B9, B8,
C9, C8, D9,
D8, E9, E1,
D2, D1, C2,
C1, B2, B1, A2
A9, E7, J9, A1,
E3, J1
A7, B3, C7, D3,
A3, B7, C3, D7
E2, G1
CS
BA0, BA1
INPUT
INPUT
A0 ~ A12
INPUT
RAS, CAS, WE
UDQM, LDQM
INPUT
INPUT
DQ0 ~ DQ15
I/O
Data Input/Output : Multiplexed data input/output pin
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
SUPPLY
SUPPLY
-
Power supply for internal circuits
Power supply for output buffers
No connection
Rev 1.0 / Jul. 2005
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