256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
11
DESCRIPTION
The Hynix HY5S5B6GLF(P) is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular
phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.
The Hynix 256M Mobile SDRAM is 268,435,456-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the
main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of
4,194,304x16.
Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch
each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the
input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16 Input/
Output bus. All the commands are latched in synchronization with the rising edge of CLK.
The Mobile SDRAMs provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8
locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is ini-
tiated at the end of the burst access. The Mobile SDRAM uses an internal pipelined architecture to achieve high-speed
operation. This architecture is compartible with the
2n
rule of prefetch architectures, but it also allows the column
address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while
accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randon-
access operation.
Read and write accesses to the Hynix Mobile SDRAMs are burst oriented;
accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be
accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and
the starting column location for the burst access. A burst of Read or Write cycles in progress can be terminated by a
burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any
cycle(This pipelined design is not restricted by a
2N
rule).
The Hynix Mobile SDR also provides for special programmable options including Partial Array Self Refresh of full array,
half array, quarter array Temperature Compensated Self Refresh of 40 or 85 degrees
o
C.
The Hynix Mobile SDR has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh) to
reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automatically
adjust refresh rate according to temperature without external EMRS command.
Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power
reduction by removing power to the memory array within each Mobile SDR. By using this feature, the system can cut
off alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout
flexibility.
All inputs are LV-CMOS compatible. Devices will have a V
DD
and V
DDQ
supply of 1.8V (nominal).
Rev 1.0 / Apr. 2006
3
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
11
FEATURES
●
Standard SDRAM Protocol
Clock Synchronization Operation
- All the commands registered on positive edge of basic input clock (CLK)
●
●
MULTIBANK OPERATION - Internal 4bank operation
- During burst Read or Write operation, burst Read or Write for a different bank is performed.
- During burst Read or Write operation, a different bank is activated and burst Read or Write
for that bank is performed
- During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
●
Power Supply Voltage : V
DD
= 1.8V, V
DDQ
= 1.8V
LVCMOS compatible I/O Interface
Low Voltage interface to reduce I/O power
Programmable burst length: 1, 2, 4, 8 or full page
Programmable Burst Type : sequential or interleaved
Programmable CAS latency of 3
Programmable Drive Strength
Low Power Features
- Programmable PASR(Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Programmable DS (Drive Strength)
- Deep Power Down Mode
-25
o
C ~ 85
o
C
Operation Temperature
- Extended Temp. : -25
o
C
~ 85
o
C
●
●
●
●
●
●
●
●
●
Package Type : 54ball, 0.8mm pitch FBGA (Lead Free, Lead), 8 x 10 [mm
2
], t=0.1mm
max
HY5S5B6GLFP : Lead Free
HY5S5B6GLF : Leaded
Rev 1.0 / Apr. 2006
4
ARM Technology
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